MT48LC16M8A2TG-7ELIT View Datasheet(PDF) - Micron Technology

Part Name

Description

Manufacturer

MT48LC16M8A2TG-7ELIT

SYNCHRONOUS DRAM

Micron Technology 

Data for any WRITE burst may be truncated with a

subsequent READ command, and data for a fixed-length

WRITE burst may be immediately followed by a READ

command. Once the READ command is registered, the

data inputs will be ignored, and WRITEs will not be

executed. An example is shown in Figure 17. Data n + 1 is

either the last of a burst of two or the last desired of a

longer burst.

Data for a fixed-length WRITE burst may be followed

by, or truncated with, a PRECHARGE command to the

same bank (provided that auto precharge was not acti-

vated), and a full-page WRITE burst may be truncated

with a PRECHARGE command to the same bank. The

PRECHARGE command should be issued tWR after the

clock edge at which the last desired input data element is

registered. The auto precharge mode requires a tWR of at

T0

T1

T2

T3

CLK

128Mb: x4, x8, x16

SDRAM

least one clock plus time, regardless of frequency.

In addition, when truncating a WRITE burst, the DQM

signal must be used to mask input data for the clock edge

prior to, and the clock edge coincident with, the

PRECHARGE command. An example is shown in Figure

18. Data n + 1 is either the last of a burst of two or the last

desired of a longer burst. Following the PRECHARGE

command, a subsequent command to the same bank

cannot be issued until tRP is met.

In the case of a fixed-length burst being executed to

completion, a PRECHARGE command issued at the opti-

mum time (as described above) provides the same op-

eration that would result from the same fixed-length

burst with auto precharge. The disadvantage of the

PRECHARGE command is that it requires that the com-

mand and address buses be available at the appropriate

time to issue the command; the advantage of the

PRECHARGE command is that it can be used to truncate

fixed-length or full-page bursts.

COMMAND

WRITE

WRITE

WRITE

WRITE

ADDRESS

BANK,

COL n

BANK,

COL a

BANK,

COL x

BANK,

COL m

DQ

DIN

n

DIN

DIN

a

x

DIN

m

NOTE: Each WRITE command may be to any bank.

DQM is LOW.

Figure 16

Random WRITE Cycles

T0

T1

T2

T3

T4

T5

CLK

COMMAND

WRITE

NOP

READ

NOP

NOP

NOP

ADDRESS

BANK,

COL n

BANK,

COL b

DQ

DIN

n

DIN

n+1

DOUT

b

DOUT

b+1

NOTE: The WRITE command may be to any bank, and the READ command may

be to any bank. DQM is LOW. CAS latency = 2 for illustration.

Figure 17

WRITE to READ

T0

T1

T2

T3

CLK

T4

T5

T6

tWR@ tCK 15ns

DQM

COMMAND

WRITE

t RP

NOP

PRECHARGE

NOP

NOP

ACTIVE

NOP

ADDRESS

DQ

BANK a,

COL n

DIN

n

BANK

(a or all)

DIN

n+1

t WR

BANK a,

ROW

tWR@ tCK < 15ns

DQM

COMMAND

WRITE

NOP

ADDRESS

BANK a,

COL n

DQ

DIN

n

DIN

n+1

NOP

PRECHARGE

t RP

NOP

NOP

BANK

(a or all)

t WR

ACTIVE

BANK a,

ROW

NOTE: DQM could remain LOW in this example if the WRITE burst is a fixed length

of two.

DON’T CARE

Figure 18

WRITE to PRECHARGE

128Mb: x4, x8, x16 SDRAM

128MSDRAM_E.p65 – Rev. E; Pub. 1/02

23

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2001, Micron Technology, Inc.

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