MT48LC16M8A2TG-7ELIT View Datasheet(PDF) - Micron Technology
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Description
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MT48LC16M8A2TG-7ELIT Datasheet PDF : 59 Pages
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WRITE with Auto Precharge
3. Interrupted by a READ (with or without auto
precharge): A READ to bank m will interrupt a WRITE
on bank n when registered, with the data-out appear-
ing CAS latency later. The PRECHARGE to bank n will
begin after tWR is met, where tWR begins when the
READ to bank m is registered. The last valid WRITE to
bank n will be data-in registered one clock prior to the
READ to bank m (Figure 26).
128Mb: x4, x8, x16
SDRAM
4. Interrupted by a WRITE (with or without auto
precharge): A WRITE to bank m will interrupt a WRITE
on bank n when registered. The PRECHARGE to bank
n will begin after tWR is met, where tWR begins when
the WRITE to bank m is registered.
The last valid data WRITE to bank n will be data
registered one clock prior to a WRITE to bank m
(Figure 27).
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
NOP
WRITE - AP
BANK n
NOP
READ - AP
NOP
BANK m
NOP
NOP
BANK n
Internal
States
BANK m
Page Active
WRITE with Burst of 4
Page Active
Interrupt Burst, Write-Back
tWR - BANK n
Precharge
tRP - BANK n
READ with Burst of 4
NOP
tRP - BANK m
ADDRESS
BANK n,
COL a
BANK m,
COL d
DQ
DIN
DIN
a
a+1
DOUT
d
DOUT
d+1
NOTE: 1. DQM is LOW.
CAS Latency = 3 (BANK m)
Figure 26
WRITE With Auto Precharge Interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
NOP
WRITE - AP
BANK n
NOP
NOP
BANK n
Internal
States
BANK m
Page Active
WRITE with Burst of 4
Page Active
WRITE - AP
NOP
NOP
NOP
BANK m
Interrupt Burst, Write-Back
tWR - BANK n
Precharge
tRP - BANK n
t WR - BANK m
WRITE with Burst of 4
Write-Back
ADDRESS
DQ
BANK n,
COL a
DIN
a
DIN
a+1
DIN
a+2
BANK m,
COL d
DIN
d
DIN
d+1
DIN
d+2
DIN
d+3
NOTE: 1. DQM is LOW.
DON’T CARE
Figure 27
WRITE With Auto Precharge Interrupted by a WRITE
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
27
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
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