MT48LC8M32B2 View Datasheet(PDF) - Micron Technology

Part Name

Description

Manufacturer

MT48LC8M32B2

SYNCHRONOUS DRAM

Micron Technology 

Burst Type

Accesses within a given burst may be programmed

to be either sequential or interleaved; this is referred to

as the burst type and is selected via bit M3.

The ordering of accesses within a burst is deter-

mined by the burst length, the burst type and the start-

ing column address, as shown in Table 1.

Figure 1

Mode Register Definition

A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus

11 10 9 8 7 6 5 4 3 2 1 0

Reserved* WB Op Mode CAS Latency BT Burst length

Mode Register (Mx)

*Should program

M10, M11, BA0,

BA1 = “0” to ensure

compatibility with

future devices.

M2 M1M0

000

001

010

011

100

101

110

111

Burst Length

M3 = 0

1

2

4

8

Reserved

Reserved

Reserved

Full Page

M3 = 1

1

2

4

8

Reserved

Reserved

Reserved

Reserved

M3

0

1

M6 M5 M4

000

001

010

011

100

101

110

111

Burst Type

Sequential

Interleave

CAS Latency

Reserved

1

2

3

Reserved

Reserved

Reserved

Reserved

M8

M7 M6 - M0 Operating Mode

0

0

Defined Standard operation

-

-

-

All other states reserved

M9

Write Burst Mode

0

Programmed Burst Length

1

Single Location Access

PRELIMINARY

256Mb: x32

SDRAM

Table 1

Burst Definition

Burst Starting Column Order of Accesses Within a Burst

Length

Address

Type = Sequential Type = Interleaved

2

4

8

Full

Page

(256)

A0

0

0-1

1

1-0

A1 A0

00

0-1-2-3

01

1-2-3-0

10

2-3-0-1

11

3-0-1-2

A2 A1 A0

0 0 0 0-1-2-3-4-5-6-7

0 0 1 1-2-3-4-5-6-7-0

0 1 0 2-3-4-5-6-7-0-1

0 1 1 3-4-5-6-7-0-1-2

1 0 0 4-5-6-7-0-1-2-3

1 0 1 5-6-7-0-1-2-3-4

1 1 0 6-7-0-1-2-3-4-5

1 1 1 7-0-1-2-3-4-5-6

n = A0–A8

Cn, Cn + 1, Cn + 2

Cn + 3, Cn + 4...

(Location 0 –256)

…Cn - 1,

Cn…

0-1

1-0

0-1-2-3

1-0-3-2

2-3-0-1

3-2-1-0

0-1-2-3-4-5-6-7

1-0-3-2-5-4-7-6

2-3-0-1-6-7-4-5

3-2-1-0-7-6-5-4

4-5-6-7-0-1-2-3

5-4-7-6-1-0-3-2

6-7-4-5-2-3-0-1

7-6-5-4-3-2-1-0

Not Supported

NOTE:

1. For a burst length of two, A1–A8 select the block-

of-two burst; A0 selects the starting column

within the block.

2. For a burst length of four, A2–A8 select the block-

of-four burst; A0–A1 select the starting column

within the block.

3. For a burst length of eight, A3–A8 select the block-

of-eight burst; A0–A2 select the starting column

within the block.

4. For a full-page burst, the full row is selected and

A0–A8 select the starting column.

5. Whenever a boundary of the block is reached

within a given sequence above, the following

access wraps within the block.

6. For a burst length of one, A0–A8 select the unique

column to be accessed, and mode register bit M3

is ignored.

09005aef80cd8e48

256MbSDRAMx32.p65 – Rev. B; Pub. 03/04

10

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2003 Micron Technology, Inc.

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