MT48LC8M32B2 View Datasheet(PDF) - Micron Technology

Part Name

Description

Manufacturer

MT48LC8M32B2

SYNCHRONOUS DRAM

Micron Technology 

PRELIMINARY

256Mb: x32

SDRAM

BALL DESCRIPTIONS

90-BALL FBGA

J1

SYMBOL

CLK

J2

CKE

J8

CS#

J9, K7, K8

K9, K1, F8, F2

RAS#, CAS#

WE#

DQM0–3

J7, H8

BA0, BA1

G8, G9, F7, F3, G1, G2,

G3, H1, H2, J3, G7, H9

A0–A11

R8, N7, R9, N8, P9, M8,

M7, L8, L2, M3, M2, P1, N2,

R1, N3, R2, E8, D7, D8, B9,

C8, A9, C7, A8, A2, C3, A1,

C2, B1, D2, D3, E2

E3, E7, H3, H7, K2, K3

DQ0–DQ31

NC

B2, B7, C9, D9, E1,

L1, M9, N9, P2, P7

B8, B3, C1, D1, E9,

L9, M1, N1, P3, P8

A7, F9, L7, R7

A3, F1, L3, R3

VDDQ

VSSQ

VDD

VSS

TYPE

DESCRIPTION

Input

Clock: CLK is driven by the system clock. All SDRAM input signals are sampled

on the positive edge of CLK. CLK also increments the internal burst counter

and controls the output registers.

Input

Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.

Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH

operation (all banks idle), ACTIVE POWER-DOWN (row active in any bank) or

CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except

after the device enters power-down and self refresh modes, where CKE

becomes asynchronous until after exiting the same mode. The input buffers,

including CLK, are disabled during power-down and self refresh modes,

providing low standby power. CKE may be tied HIGH.

Input

Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the

command decoder. All commands are masked when CS# is registered HIGH. CS#

provides for external bank selection on systems with multiple banks. CS# is

considered part of the command code.

Input Command Inputs: RAS#, CAS#, and WE# (along with CS#) define the

command being entered.

Input

Input/Output Mask: DQM is sampled HIGH and is an input mask signal for write

accesses and an output enable signal for read accesses. Input data is masked

during a WRITE cycle. The output buffers are placed in a High-Z state (two-

clock latency) when during a READ cycle. DQM0 corresponds to DQ0–DQ7,

DQM1 corresponds to DQ8–DQ15, DQM2 corresponds to DQ16–DQ23 and DQM3

corresponds to DQ24–DQ31. DQM0-3 are considered same state when

referenced as DQM.

Input

Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ,

WRITE or PRECHARGE command is being applied. These pins also provide the

op-code during a LOAD MODE REGISTER command

Input

Address Inputs: A0–A11 are sampled during the ACTIVE command (row-

address A0–A11) and READ/WRITE command (column-address A0–A8; with A10

defining auto precharge) to select one location out of the memory array in the

respective bank. A10 is sampled during a PRECHARGE command to determine if

all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1 (LOW).

The address inputs also provide the op-code during a LOAD MODE REGISTER

command.

I/O Data Input/Output: Data bus

–

Supply

No Connect: These pins should be left unconnected.

H3 is a not connect for this part but may be used as A12 in future designs.

DQ Power: Provide isolated power to DQs for improved noise immunity.

Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity.

Supply Power Supply: Voltage dependant on option.

Supply Ground.

09005aef80cd8e48

256MbSDRAMx32.p65 – Rev. B; Pub. 03/04

8

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2003 Micron Technology, Inc.

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