NT5SV16M16AT View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

NT5SV16M16AT

256Mb Synchronous DRAM

Unspecified 

NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

Read Interrupted by a Write

To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output drivers) in a high impedance

state to avoid data contention on the DQ bus. If a Read Command will issue data on the first or second clocks cycles of the

write operation, DQM is needed to insure the DQs are tri-stated. After that point the Write Command will have control of the DQ

bus.

Minimum Read to Write Interval

(Burst Length = 4, CAS latency = 2, 3)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK

DQM

DQM high for CAS latency = 2 only.

Required to mask first bit of READ data.

COMMAND NOP

READ A

WRITE A

NOP

NOP

NOP

CAS latency = 2

t CK2, DQs

CAS latency = 3

t CK3, DQs

: “H” or “L”

DIN A 0

DIN A 1

DIN A 2

DIN A 3

DIN A 0

DIN A 1

DIN A 2

DIN A 3

NOP

NOP

NOP

REV 1.0

May, 2001

12

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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

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