NT5SV16M16AT View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

NT5SV16M16AT

256Mb Synchronous DRAM

Unspecified 

NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

Non-Minimum Write to Read Interval

(Burst Length = 4, CAS latency = 2, 3)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK

COMMAND WRITE A

NOP

READ B

NOP

CAS latency = 2

tCK2, DQs

DIN A 0

CAS latency = 3

tCK3, DQs

DIN A0

DIN A 1

DIN A 1

NOP

NOP

NOP

NOP

NOP

DOUT B0

DOUT B 1

DOUT B2

DOUT B 3

DOUT B 0

DOUT B1

DOUT B2

DOUT B 3

: “H” or “L”

Input data for the Write is masked.

Input data must be removed from the DQs at least one clock

cycle before the Read data appears on the outputs to avoid

data contention.

REV 1.0

May, 2001

16

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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

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