P89V51RB2BA View Datasheet(PDF) - Philips Electronics

Part Name

Description

Manufacturer

P89V51RB2BA

8-bit 80C51 5 V low power 16/32/64 kB Flash microcontroller with 1 kB RAM

Philips Electronics 

Philips Semiconductors

P89V51RB2/RC2/RD2

8-bit microcontrollers with 80C51 core

7. Functional description

7.1 Memory organization

The device has separate address spaces for program and data memory.

7.1.1 Flash program memory bank selection

There are two internal flash memory blocks in the device. Block 0 has 16/32/64 kB

and is organized as 128/256/512 sectors, each sector consists of 128 Bytes. Block 1

contains the IAP/ISP routines and may be enabled such that it overlays the first 8 kB

of the user code memory. The overlay function is controlled by the combination of the

Software Reset Bit (SWR) at FCF.1 and the Bank Select Bit (BSEL) at FCF.0. The

combination of these bits and the memory source used for instructions is shown in

Table 5.

Table 5: Code memory bank selection

SWR (FCF.1)

BSEL (FCF.0)

addresses from 0000h

to 1FFFh

0

0

Bootcode (in Block 1)

0

1

User code (in Block 0)

1

0

1

1

addresses above 1FFFh

User code (in Block 0)

Access to the IAP routines in Block 1 may be enabled by clearing the BSEL bit

(FCF.0), provided that the SWR bit (FCF.1) is cleared. Following a power-on

sequence, the bootcode is automatically executed and attempts to autobaud to a

host. If no autobaud occurs within approximately 400 ms and the SoftICE flag is not

set, control will be passed to the user code. A software reset is used to accomplish

this control transfer and as a result the SWR bit will remain set. Therefore the user's

code will need to clear the SWR bit in order to access the IAP routines in Block

1. However, caution must be taken when dynamically changing the BSEL bit. Since

this will cause different physical memory to be mapped to the logical program

address space, the user must avoid clearing the BSEL bit when executing user code

within the address range 0000H to 1FFFH.

7.1.2 Power-on reset code execution

At initial power up, the port pins will be in a random state until the oscillator has

started and the internal reset algorithm has weakly pulled all pins high. Powering up

the device without a valid reset could cause the MCU to start executing instructions

from an indeterminate location. Such undefined states may inadvertently corrupt the

code in the flash. A system reset will not affect the 1 kB of on-chip RAM while the

device is running, however, the contents of the on-chip RAM during power up are

indeterminate.

When power is applied to the device, the RST pin must be held high long enough for

the oscillator to start up (usually several milliseconds for a low frequency crystal), in

addition to two machine cycles for a valid power-on reset. An example of a method to

extend the RST signal is to implement a RC circuit by connecting the RST pin to VDD

through a 10 F capacitor and to VSS through an 8.2KW resistor as shown in

9397 750 14341

Product data

Rev. 03 — 02 December 2004

© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

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