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P89V51RB2BA View Datasheet(PDF) - Philips Electronics

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P89V51RB2BA Datasheet PDF : 77 Pages
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Philips Semiconductors
P89V51RB2/RC2/RD2
8-bit microcontrollers with 80C51 core
When EXTRAM = 0, the expanded RAM is indirectly addressed using the MOVX
instruction in combination with any of the registers R0, R1 of the selected bank or
DPTR. Accessing the expanded RAM does not affect ports P0, P3.6 (WR), P3.7
(RD), or P2. With EXTRAM = 0, the expanded RAM can be accessed as in the
following example.
Expanded RAM Access (Indirect Addressing only):
MOVX@DPTR, A DPTR contains 0A0H
DPTR points to 0A0H and data in ‘A’ is written to address 0A0H of the expanded
RAM rather than external memory. Access to external memory higher than 2FFH
using the MOVX instruction will access external memory (0300H to FFFFH) and will
perform in the same way as the standard 8051, with P0 and P2 as data/address bus,
and P3.6 and P3.7 as write and read timing signals.
When EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard
8051. Using MOVX @Ri provides an 8-bit address with multiplexed data on Port 0.
Other output port pins can be used to output higher order address bits. This provides
external paging capabilities. Using MOVX @DPTR generates a 16-bit address. This
allows external addressing up the 64 kB. Port 2 provides the high-order eight address
bits (DPH), and Port 0 multiplexes the low order eight address bits (DPL) with data.
Both MOVX @Ri and MOVX @DPTR generates the necessary read and write
signals (P3.6 - WR and P3.7 - RD) for external memory use. Table 9 shows external
data memory RD, WR operation with EXTRAM bit.
The stack pointer (SP) can be located anywhere within the 256 bytes of internal RAM
(lower 128 bytes and upper 128 bytes). The stack pointer may not be located in any
part of the expanded RAM.
Table 9: External data memory RD, WR with EXTRAM bit
AUXR
MOVX @DPTR, A or MOVX A,
@DPTR
MOVX @Ri, A or MOVX A, @Ri
ADDR < 0300H ADDR 0300H ADDR = any
EXTRAM = 0
RD/WR not
asserted
RD/WR asserted RD/WR not asserted
EXTRAM = 1
RD/WR asserted RD/WR asserted RD/WR asserted
[1] Access limited to ERAM address within 0 to 0FFH; cannot access 100H to 02FFH.
9397 750 14341
Product data
Rev. 03 — 02 December 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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