ICS1889 View Datasheet(PDF) - Integrated Circuit Systems

Part Name

Description

Manufacturer

ICS1889

100Base-FX Integrated PHYceiver™

Integrated Circuit Systems 

Isolate (bit 10)

Setting this bit to a logic one causes the ICS1889 to isolate its

data paths from the MII. In this mode, sourced signals

(TXCLK, RXCLK, RXDV, RXER, RXD0-3, COL and CRS)

are in a high impedance state and input signals (TXD0-3,

TXEN and TXER) are ignored. The management interface is

unaffected by this command.

When the PHY address is set to 0, the device will power-up in

the isolated mode (bit 10=1). For all other addresses, the

default will be bit 10 = 0.

Restart Auto-Negotiation (bit 9)

This feature is not available with fiber optic solutions. This

bit is permanently set to a logic zero indicating that it is not

supported.

Duplex Mode (bit 8)

Setting this bit to a logic one causes the ICS1889 to operate in

the full duplex mode and setting this bit to a logic zero causes

it to operate in the half duplex mode. If the ICS1889 is

operating in loop back mode, this bit will have no effect on

the operation.

Collision Test (bit 7)

This command bit is used to test that the collision circuitry is

working when the ICS1889 is operating in the loop back

mode. Setting this bit to a logic one causes the ICS1889 to

assert the collision signal within 512 bit times of TXEN being

asserted and to de-assert it within 4-bit times of TXEN being

de-asserted. Setting this bit to a logic zero causes the

ICS1889 to operate in the normal mode.

Reserved (Bits 6 through 0)

These bits are reserved for future IEEE standards. When read,

logic zeroes are returned. Writing has no effect on ICS1889

operation.

9

ICS1889

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