PIC16LCR65AT-04E/TQ View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16LCR65AT-04E/TQ

8-Bit CMOS Microcontrollers

Microchip Technology 

PIC16C6X

4.2.2 SPECIAL FUNCTION REGISTERS:

The Special Function Registers are registers used by

the CPU and peripheral modules for controlling the

desired operation of the device. These registers are

implemented as static RAM.

The special function registers can be classified into two

sets (core and peripheral). The registers associated

with the “core” functions are described in this section

and those related to the operation of the peripheral fea-

tures are described in the section of that peripheral fea-

ture.

TABLE 4-1: SPECIAL FUNCTION REGISTERS FOR THE PIC16C61

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on:

POR

Value on

all other

resets(3)

Bank 0

00h(1) INDF

01h

TMR0

02h(1) PCL

03h(1) STATUS

04h(1) FSR

05h

PORTA

06h

PORTB

07h

—

08h

—

09h

—

0Ah(1,2) PCLATH

0Bh(1) INTCON

Bank 1

80h(1) INDF

81h

OPTION

82h(1) PCL

83h(1) STATUS

84h(1) FSR

85h

TRISA

86h

TRISB

87h

–

88h

–

89h

–

Addressing this location uses contents of FSR to address data memory (not a physical register)

Timer0 module’s register

Program Counter's (PC) Least Significant Byte

IRP(4)

RP1(4)

RP0

TO

PD

Z

DC

C

Indirect data memory address pointer

—

—

— PORTA Data Latch when written: PORTA pins when read

PORTB Data Latch when written: PORTB pins when read

Unimplemented

Unimplemented

Unimplemented

—

—

—

Write Buffer for the upper 5 bits of the Program Counter

GIE

—

T0IE

INTE

RBIE

T0IF

INTF

RBIF

Addressing this location uses contents of FSR to address data memory (not a physical register)

RBPU INTEDG T0CS

T0SE

PSA

PS2

PS1

PS0

Program Counter's (PC) Least Significant Byte

IRP(4)

RP1(4)

RP0

TO

PD

Z

DC

C

Indirect data memory address pointer

—

—

— PORTA Data Direction Register

PORTB Data Direction Control Register

Unimplemented

Unimplemented

Unimplemented

0000 0000 0000 0000

xxxx xxxx uuuu uuuu

0000 0000 0000 0000

0001 1xxx 000q quuu

xxxx xxxx uuuu uuuu

---x xxxx ---u uuuu

xxxx xxxx uuuu uuuu

—

—

—

—

—

—

---0 0000 ---0 0000

0-00 000x 0-00 000u

0000 0000 0000 0000

1111 1111 1111 1111

0000 0000 0000 0000

0001 1xxx 000q quuu

xxxx xxxx uuuu uuuu

---1 1111 ---1 1111

1111 1111 1111 1111

—

—

—

—

—

—

8Ah(1,2) PCLATH

—

—

—

Write Buffer for the upper 5 bits of the Program Counter

---0 0000 ---0 0000

8Bh(1) INTCON

GIE

—

T0IE

INTE

RBIE

T0IF

INTF

RBIF 0-00 000x 0-00 000u

Legend:

Note 1:

2:

3:

4:

x = unknown, u = unchanged, q = value depends on condition, - = unimplemented locations read as '0'.

Shaded locations are unimplemented and read as ‘0’

These registers can be addressed from either bank.

The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose con-

tents are transferred to the upper byte of the program counter. (PC<12:8>)

Other (non power-up) resets include external reset through MCLR and the Watchdog Timer Reset.

The IRP and RP1 bits are reserved on the PIC16C61, always maintain these bits clear.

© 1997 Microchip Technology Inc.

DS30234D-page 23

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