PIC16LCR65AT-04E/TQ View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16LCR65AT-04E/TQ

8-Bit CMOS Microcontrollers

Microchip Technology 

PIC16C6X

TABLE 4-2: SPECIAL FUNCTION REGISTERS FOR THE PIC16C62/62A/R62

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on:

POR,

BOR

Value on

all other

resets(3)

Bank 0

00h(1) INDF

Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000

01h

TMR0

Timer0 module’s register

xxxx xxxx uuuu uuuu

02h(1) PCL

Program Counter's (PC) Least Significant Byte

0000 0000 0000 0000

03h(1) STATUS

IRP(5)

RP1(5)

RP0

TO

PD

Z

DC

C

0001 1xxx 000q quuu

04h(1) FSR

Indirect data memory address pointer

xxxx xxxx uuuu uuuu

05h

PORTA

—

— PORTA Data Latch when written: PORTA pins when read

--xx xxxx --uu uuuu

06h

PORTB PORTB Data Latch when written: PORTB pins when read

xxxx xxxx uuuu uuuu

07h

PORTC PORTC Data Latch when written: PORTC pins when read

xxxx xxxx uuuu uuuu

08h

—

Unimplemented

—

—

09h

—

Unimplemented

—

—

0Ah(1,2) PCLATH

—

—

— Write Buffer for the upper 5 bits of the Program Counter

---0 0000 ---0 0000

0Bh(1) INTCON

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF 0000 000x 0000 000u

0Ch

PIR1

(6)

(6)

—

—

SSPIF CCP1IF TMR2IF TMR1IF 00-- 0000 00-- 0000

0Dh

—

Unimplemented

—

—

0Eh

TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register

xxxx xxxx uuuu uuuu

0Fh

TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register

xxxx xxxx uuuu uuuu

10h

T1CON

—

—

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu

11h

TMR2

Timer2 module’s register

0000 0000 0000 0000

12h

T2CON

—

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

13h

SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register

xxxx xxxx uuuu uuuu

14h

SSPCON WCOL SSPOV SSPEN

CKP

SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000

15h

CCPR1L Capture/Compare/PWM1 (LSB)

xxxx xxxx uuuu uuuu

16h

CCPR1H Capture/Compare/PWM1 (MSB)

xxxx xxxx uuuu uuuu

17h

CCP1CON

—

—

CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

18h-1Fh

—

Unimplemented

—

—

Legend:

Note 1:

2:

3:

4:

5:

6:

x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'.

Shaded locations are unimplemented, read as ‘0’.

These registers can be addressed from either bank.

The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose

contents are transferred to the upper byte of the program counter. (PC<12:8>)

Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset.

The BOR bit is reserved on the PIC16C62, always maintain this bit set.

The IRP and RP1 bits are reserved on the PIC16C62/62A/R62, always maintain these bits clear.

PIE1<7:6> and PIR1<7:6> are reserved on the PIC16C62/62A/R62, always maintain these bits clear.

DS30234D-page 24

© 1997 Microchip Technology Inc.

Share Link: