MTV212AN32 View Datasheet(PDF) - Myson Century Inc

Part Name

Description

Manufacturer

MTV212AN32

8051 Embedded Monitor Controller Mask ROM Type

Myson Century Inc 

MYSON

TECHNOLOGY

MTV212A32

(Rev. 1.2)

= 0 → Current transfer is slave receive

SAckIn = 1 → The external IIC host respond NACK.

SLVS = 1 → The slave block has detected a START, cleared when STOP detected.

SlvAlsb1,SlvAlsb0 : The 2 LSB which host send to Slave A block.

MAckIn = 1 → Master IIC bus error, no ACK received from the slave IIC device.

= 0 → ACK received from the slave IIC device.

Hifreq = 1 → MTV212A32 has detected a higher than 200Hz clock on the VSYNC pin.

Hbusy = 1

→ Host drives the HSCL pin to low.

INTFLG (w) : Interrupt flag. A interrupt event will set its individual flag, and, if the corresponding interrupt

enable bit is set, the 8051 INT1 source will be driven by a zero level. Software MUST clear

this register while serve the interrupt routine.

SlvBMI = 1 → No action.

= 0 → Clear SlvBMI flag.

SlvAMI = 1 → No action.

= 0 → Clear SlvAMI flag.

MbufI = 1 → No action.

= 0 → Clear Master IIC bus interrupt flag (MbufI).

INTFLG (r) : Interrupt flag.

TXBI = 1 → Indicates the TXBBUF need a new data byte, clear by writing TXBBUF.

RCBI = 1 → Indicates the RCBBUF has received a new data byte, clear by reading RCBBUF.

SlvBMI = 1 → Indicates the slave IIC address B match condition.

TXAI = 1 → Indicates the TXABUF need a new data byte, clear by writing TXABUF.

RCAI = 1 → Indicates the RCABUF has received a new data byte, clear by reading RCABUF.

SlvAMI = 1 → Indicates the slave IIC address A match condition.

DbufI = 1 → Indicates the DDC1 data buffer need a new data byte, clear by writing DBUF.

MbufI = 1 → Indicates a byte is sent/received to/from the master IIC bus.

INTEN (w) : Interrupt enable.

ETXBI = 1 → Enable TXBBUF interrupt.

ERCBI = 1 → Enable RCBBUF interrupt.

ESlvBMI = 1 → Enable slave address B match interrupt.

ETXAI = 1 → Enable TXABUF interrupt.

ERCAI = 1 → Enable RCABUF interrupt.

ESlvAMI = 1 → Enable slave address A match interrupt.

EDbufI = 1 → Enable DDC1 data buffer interrupt.

EMbufI = 1 → Enable Master IIC bus interrupt.

Mbuf (w) :

Master IIC data shift register, after START and before STOP condition, write this register will

resume MTV212A32's transmission to the IIC bus.

Mbuf (r) :

Master IIC data shift register, after START and before STOP condition, read this register will

resume MTV212A32's receiving from the IIC bus.

RCABUF (r) : Slave IIC block A receive data buffer.

TXABUF (w) : Slave IIC block A transmit data buffer.

SLVAADR (w) : Slave IIC block A's enable and address.

ENslvA = 1 → Enable slave IIC block A.

= 0 → Disable slave IIC block A.

bit6-0 :

Slave IIC address A to which the slave block should respond.

Revision 1.2

- 17 -

2000/07/04

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