RF2705 View Datasheet(PDF) - RF Micro Devices

Part Name

Description

Manufacturer

RF2705

QUADRATURE DEMODULATOR

RF Micro Devices 

RF2705

Pin

4

5

6

Function

LO LB P

LO LB N

MODE C

Description

Interface Schematic

Low band local oscillator input (900MHz).

In “wideband FLOx2” and “high band FLOx2” modes the signal

(LOLBP-LOLBN) is doubled in frequency to provide the LO signal for

the modulator.

In “Low band FLOx1” modes the signal (LOLBP-LOLBN) is used as

the LO signal for the modulator.

VCC

In “Low band Bypass” a modulated GSM900 signal (LOLBP-LOLBN)

is switched into the RF signal path. The modulator is disabled and the

signal is routed to the RFOutLb outputs through a differential PA driver

amplifier.

This LOLBP input is AC-coupled internally.

The noise performance, carrier suppression at low output powers and LO LB P

sideband suppression performance are functions of LO power. The

optimum LO power is between -3dBm and +3dBm. The device will

work with LO powers as low as -20dBm however this is at the expense LO LB N

of higher noise performance at high output powers and poorer side-

band suppression.

The input impedance should be externally matched to 50Ω. The port

impedance does not vary significantly between active and powered

modes.

The RF2705 is intended for use with the RF6002 which performs the

GSM GMSK modulation within a Frac-N synthesizer loop. The 8PSK

EDGE and W-CDMA signal modulations are performed in the RF2705

and uses the RF6002’s synthesizers to generate the LO signals. The

LO signal for DCS1800 mode is derived by frequency doubling

RF6002’s GSM900 VCO. This helps protect the system against PA pull-

ing.

The complementary LO input for both LOLBP LO signals.

In any of the modes the LOLB input may be driven either single ended

or differentially. If the LO is driven single ended then the PCB board

designer can ground this pin.

It is recommended that if this pin is grounded that it is kept isolated

from the GND1 pin and the die flag ground. All connections to any other

ground should be made through a ground plane. Poor routing of this

GndLO signal can significantly degrade the LO leakage performance.

See pin 4.

Chip enable control pin. See the Logic Truth table.

CMOS Logic inputs: Logic 0=0V to 0.4V; Logic 1=1.4V to VCC.

VCC2

7

MODE D Mode control pin. See the Logic Truth table.

CMOS Logic inputs: Logic 0=0V to 0.4V; Logic 1=1.4V to VCC.

See pin 6.

Rev A4 041026

5-125

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