S25FL208K View Datasheet(PDF) - Spansion Inc.
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S25FL208K Datasheet PDF : 37 Pages
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Data Sheet (Preliminary)
signal to the logic low state does not terminate any Write, Program or Erase operation that is currently in
progress.
During the Hold condition, SO is in high impedance and both the SI and SCK input are Don't Care. The Hold
condition ends on the rising edge of the Hold (HOLD#) signal, provided that this coincides with the SCK signal
being at the logic low state. If the rising edge does not coincide with the SCK signal being at the logic low
state, the Hold condition ends whenever the SCK signal reaches the logic low state.
SC K
HO LD #
Figure 6.2 Hold Condition Waveform
A c tiv e
H o ld
A c tiv e
H o ld
A c tiv e
6.4
Status Register
The Status Register contains a number of status and control bits that can be read or set (as appropriate) by
specific instructions
Table 6.1 Status Register Bit Locations
R7
R6
R5
R4
R3
R2
R1
R0
SRP
REV
BP3
BP2
BP1
BP0
WEL
WIP
Write in Progress (WIP) is a read only bit in the status register (R0) which indicates whether the device is
performing a program, write, erase operation, or any other operation, during which a new operation
command will be ignored. When the WIP bit is set to 1, the device is busy performing an operation. When
the bit is cleared to 0, no operation is in progress.
Write Enable Latch (WEL) is a read only bit in the status register (R1) that must be set to 1 to enable
program, write, or erase operations as a means to provide protection against inadvertent changes to
memory or register values. The Write Enable (WREN) command execution sets the Write Enable Latch to
a 1 to allow any program, erase, or write commands to execute afterwards. The Write Disable (WRDI)
command can be used to set the Write Enable Latch to a 0 to prevent all program, erase, and write
commands from execution. The WEL bit is cleared to 0 at the end of any successful program, write, or
erase operation. After a power down/power up sequence, hardware reset, or software reset, the Write
Enable Latch is set to a 0.
Block Protect Bits (BP3, BP2, BP1, BP0) are non-volatile read/write bits in the status register (R5, R4,
R3, and R2) that define the main flash array area to be software protected against program and erase
commands. When one or more of the BP bits is set to 1, the relevant memory area is protected against
program and erase. The Chip Erase (CE) command can be executed only when the BP bits are cleared to
0’s. See Table 7.1 on page 13 for a description of how the BP bit values select the memory array area
protected. The factory default setting for all the BP bits is 0, which implies that none of array is protected.
Reserved Bits (REV), Status register bit location R6 is reserved for future use. Current devices will read 0
for this bit location. It is recommended to mask out the reserved bit when testing the Status Register. Doing
this will ensure compatibility with future devices.
The Status Register Protect (SRP) bit is a non-volatile read/write bit in status register (R7) that can be
used in conjunction with the Write Protect (WP#) pin to disable writes to status register. When the SRP bit
is set to a 0 state (factory default) the WP# pin has no control over status register. When the SRP pin is set
12
S25FL208K
S25FL208K_00_05 August 14, 2012
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