FL208KIF View Datasheet(PDF) - Spansion Inc.

Part Name

Description

Manufacturer

FL208KIF

8-Mbit 3.0V Serial Flash Memory with Uniform 4 kB Sectors

Spansion Inc. 

Data Sheet (Preliminary)

Figure 8.4 Write Status Register Command Sequence

CS#

Mode3

SC K M ode0

SI/IO0

SO

*= M SB

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Mode3

Mode0

Instruction (01H )

7 654 3 21 0

*

High Im pedance

8.5

Read Data (03h)

The Read Data command allows one more data bytes to be sequentially read from the memory. The

command is initiated by driving the CS# pin low and then shifting the instruction code “03h” followed by a

24-bit address (A23-A0) into the SI/IO0 pin. The code and address bits are latched on the rising edge of the

SCK pin. After the address is received, the data byte of the addressed memory location will be shifted out on

the SO pin at the falling edge of SCK with most significant bit (MSB) first. The address is automatically

incremented to the next higher address after each byte of data is shifted out allowing for a continuous stream

of data. This means that the entire memory can be accessed with a single command as long as the clock

continues. The command is completed by driving CS# high.

The Read Data command sequence is shown in Figure 8.5. If a Read Data command is issued while an

Erase, Program or Write cycle is in process (WIP=1) the command is ignored and will not have any effects on

the current cycle. The Read Data command allows clock rates from D.C. to a maximum of fR. See AC

Characteristics on page 31.

Figure 8.5 Read Data Command Sequence

CS#

Mode3 0 1 2 3 4 5 6 7 8 9 10

SC K M ode0

28 29 30 31 32 33 34 35 36 37 38 39

SI/IO0

SO

*=M SB

Instruction (03H)

24-Bit Address

23 22 21

*

High Im pedance

321 0

Data O ut 1

Data O ut 2

7 6 54 321 07

*

8.6

Fast Read (0Bh)

The Fast Read command is similar to the Read Data command except that it can operate at higher frequency

than the traditional Read Data command. See AC Characteristics on page 31. This is accomplished by

adding eight “dummy” clocks after the 24-bit address as shown in Figure 8.6. The dummy clocks allow the

device’s internal circuits additional time for setting up the initial address. During the dummy clocks the data

value on the SI pin is a “don’t care”.

18

S25FL208K

S25FL208K_00_05 August 14, 2012

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