S5L9284 View Datasheet(PDF) - Samsung

Part Name

Description

Manufacturer

S5L9284

DIGITAL SIGNAL PROCESSOR

Samsung 

DIGITAL SIGNAL PROCESSOR

S5L9284D

FRAME SYNC DETECTOR, PROTECTOR AND INSERTER

A. Frame Sync Detector

The data consists of frame units, which include frame sync, subcode data, PCM data, redundancy data, etc. The

frame sync is detected in order to maintain the sync.

B. Frame Sync Protector/Inserter

Occasionally, the frame sync is omitted or detected in a place where it doesn’t exist by the effect of error or jitter on

a disc.

In these cases, we need to protect or insert the signal. A window is made to protect the frame sync by using the

WSEL. If the frame sync is input to the window, it is true data, and if isn't input, it is ignored. The width of the

window is determined by WSEL of the CNTL-S register. If the frame sync is not detected in the frame sync

protection window, one sync which is made by the internal counter block, is inserted in sequence. When the

appointed number of frames is achieved by FSEM, FSEL of the CNTL-S register, the ULKFS becomes “L” and the

frame sync protection window is ignored. The frame sync is received absolutely at that time. When the frame sync

is received, the ULKFS signal becomes “H” and the frame sync window is received.

LKFS

1

0

0

ULKFS

Comment

1

Corresponding with playback frame sync and generated frame sync

1

1. Out of correspondence with playback frame sync generated frame sync, but PBFR sync

is detected in the window selected by WSEL.

2. Out of correspondence with PBFR sync and XTFR sync, and sync is inserted because it

isn’t detected in the window selected by WSEL.

0

1. After inserting as many frames as decided by FSEM and FSEL of the CNTL-S register,

and the window is ignored.

2. In case that the PBFR sync is not detected continually after (1).

SUBCODE BLOCK

The subcode sync signal (that is S0, S1) is detected in the subcode sync block. When S0 is detected, S1 is

detected after one frame. At that time, the S0 + S1 signal is output to the S0S1 terminal, and the S0S1 signal is

output to the SBDT terminal when the S0S1 signal is “H”. The subcode data among the data input to the EFM

terminal, is demodulated to 8-bit subcode data (P, Q, R, S,T, U, V, W). It is synchronized with the PBFR signal and

is output to SBDT by the SBCK clock. Among the eight subcode data, only Q data is selected and loaded to the

eighty shift register by the PBFR signal. The result of the CRC (Cycle Redundancy Check) of loading data, is

synchronized with the S0S1 positive edge and output to the SQOK terminal.

If the result is error, “L” is output to the SQOK terminal, and if it is true, “H” is output instead.

If the CRCD of CNTL-Z mode is “H”, the result of CRC checking is output to the SQDT terminal from the S0S1

section “H” to the period of the SQCK negative edge.

The following is the timing chart of the subcode block

15

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