SST25VF020B-80-4I-SAE View Datasheet(PDF) - Silicon Storage Technology

Part Name

Description

Manufacturer

SST25VF020B-80-4I-SAE

2 Mbit SPI Serial Flash

Silicon Storage Technology 

Data Sheet

Write-Status-Register (WRSR)

The Write-Status-Register instruction writes new values to

the BP1, BP0, and BPL bits of the status register. CE#

must be driven low before the command sequence of the

WRSR instruction is entered and driven high before the

WRSR instruction is executed. See Figure 20 for EWSR or

WREN and WRSR for byte-data input sequences.

Executing the Write-Status-Register instruction will be

ignored when WP# is low and BPL bit is set to “1”. When

the WP# is low, the BPL bit can only be set from “0” to “1” to

lock-down the status register, but cannot be reset from “1”

to “0”. When WP# is high, the lock-down function of the

2 Mbit SPI Serial Flash

SST25VF020B

BPL bit is disabled and the BPL, BP0, and BP1 bits in the

status register can all be changed. As long as BPL bit is set

to 0 or WP# pin is driven high (VIH) prior to the low-to-high

transition of the CE# pin at the end of the WRSR instruc-

tion, the bits in the status register can all be altered by the

WRSR instruction. In this case, a single WRSR instruction

can set the BPL bit to “1” to lock down the status register as

well as altering the BP0, BP1, and BP2 bits at the same

time. See Table 2 for a summary description of WP# and

BPL functions.

CE#

MODE 3 0 1 2 3 4 5 6 7

MODE 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

SCK MODE 0

MODE 0

SI

50 or 06

MSB

SO

01

MSB

HIGH IMPEDANCE

STATUS

REGISTER IN

76543210

MSB

1417 EWSR.0

FIGURE 20: Enable-Write-Status-Register (EWSR) or

Write-Enable (WREN) and Write-Status-Register (WRSR) Byte-Data Input Sequence

The Write-Status-Register instruction also writes new val-

ues to the Status Register 1. To write values to Status

Register 1, the WRSR sequence needs a word-data

input—the first byte being the Status Register bits, followed

by the second byte Status Register 1 bits. CE# must be

driven low before the command sequence of the WRSR

instruction is entered and driven high before the WRSR

instruction is executed. See Figure 21 for EWSR or WREN

and WRSR instruction word-data input sequences.

Executing the Write-Status-Register instruction will be

ignored when WP# is low and BPL bit is set to ‘1’. When

the WP# is low, the BPL bit can only be set from ‘0’ to ‘1’ to

lock-down the status registers, but cannot be reset from ‘1’

to ‘0’. When WP# is high, the lock-down function of the BPL

bit is disabled and the BPL, BP0, BP1, TSP, and BSP bits

in the status register can all be changed. As long as BPL bit

is set to 0 or WP# pin is driven high (VIH) prior to the low-to-

high transition of the CE# pin at the end of the WRSR

instruction, the bits in the status register can all be altered

by the WRSR instruction. In this case, a single WRSR

instruction can set the BPL bit to “1” to lock down the status

register as well as altering the BPL, BP0, BP1, TSP, and

BSP bits at the same time. See Table 2 for a summary

description of WP# and BPL functions.

©2010 Silicon Storage Technology, Inc.

20

S71417-02-000

04/10

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