ST10F271 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST10F271 Datasheet PDF : 173 Pages
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ST10F271
Internal Flash memory
5.2.3
Note:
Table 6. Control register interface
Name
Description
Addresses
Size
Bus
size
FCR1-0
Flash Control Registers 1-0
0x0008 0000 - 0x0008 0007 8 byte
FDR1-0
Flash Data Registers 1-0
0x0008 0008 - 0x0008 000F 8 byte
FAR
FER
Flash Address Registers
Flash Error Register
0x0008 0010 - 0x0008 0013 4 byte
0x0008 0014 - 0x0008 0015 2 byte
FNVWPIR
FNVAPR0
Flash Non Volatile Protection I
Register
0x0008 DFB0 - 0x0008
DFB1
Flash Non Volatile Access Protection 0x0008 DFB8 - 0x0008
Register 0
DFB9
2 byte
16-bit
2 byte
FNVAPR1
Flash Non Volatile Access Protection 0x0008 DFBC - 0x0008
Register 1
DFBF
4 byte
XFVTAUR0
XBus Flash Volatile Temporary
Access Unprotection Register 0
0x0000 EB50 - 0x0000 EB51 2 byte
Low power mode
The Flash module is automatically switched off executing PWRDN instruction. The
consumption is drastically reduced, but exiting this state can require a long time (tPD).
Recovery time from Power Down mode for the Flash modules is anyway shorter than the
main oscillator start-up time. To avoid any problem in restarting to fetch code from the Flash,
it is important to size properly the external circuit on RPD pin.
PWRDN instruction must not be executed while a Flash program/erase operation is in
progress.
5.3
Write operation
The Flash module have one single register interface mapped in the memory space of the
IBUS (0x08 0000 to 0x08 0015). All the operations are enabled through four 16-bit control
registers: Flash Control Register 1-0 High/Low (FCR1H/L-FCR0H/L). Eight other 16-bit
registers are used to store Flash Address and Data for Program operations (FARH/L and
FDR1H/L-FDR0H/L) and Write Operation Error flags (FERH/L). All registers are accessible
with 8 and 16-bit instructions (since operates in 16-bit mode when in read/ write).
Before accessing the IFlash module (and consequently also the Flash register to be used for
program/erasing operations), bit ROMEN in SYSCON register shall be set.
During a Flash write operation any attempt to read the flash itself, that is under modification,
will output invalid data (software trap 009Bh). This means that the Flash is not fetchable
when a programming operation is active: the write operation commands must be executed
from another memory (internal RAM or external memory), as in ST10F269 device. In fact,
due to IBUS characteristics, it is not possible to perform a write operation on IFLASH, when
fetching code from IFLASH.
Direct addressing is not allowed for write accesses to IFLASH Control Registers.
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