F271-AEA-P View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
F271-AEA-P Datasheet PDF : 180 Pages
| |||
ST10F271B/ST10F271E
Electrical characteristics
24.8.19
External bus arbitration
VDD = 5V ± 10%, VSS = 0V, TA = -40 to +125°C, CL = 50pF
Table 80. External bus arbitration timings
Symbol
Parameter
FCPU = 40 MHz
TCL = 12.5 ns
min.
max.
t61 SR
HOLD input setup time
to CLKOUT
18.5
t62 CC
CLKOUT to HLDA high
or BREQ low delay
–
t63 CC
CLKOUT to HLDA low
or BREQ high delay
–
t64 CC
CSx release 1)
–
t65 CC
CSx drive
–4
t66 CC
Other signals release 1)
–
t67 CC
Other signals drive
–4
–
12.5
12.5
20
15
20
15
1. Partially tested, guaranteed by design characterization.
Variable CPU Clock
1/2 TCL = 1 to 64MHz
min.
max.
18.5
–
ns
–
12.5
ns
–
12.5
ns
–
20
ns
–4
15
ns
–
20
ns
–4
15
ns
Figure 59. External bus arbitration (releasing the bus)
CLKOUT
t61
HOLD
HLDA
BREQ
CSx
(P6.x)
Others
t63
1)
t62
2)
t64 3)
1)
t66
1. The ST10F271 will complete the currently running bus cycle before granting bus access.
2. This is the first possibility for BREQ to become active.
3. The CS outputs will be resistive high (pull-up) after t64.
171/180
Share Link: 