F271-AEA-P View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

F271-AEA-P

16-bit MCU with 128 Kbyte Flash memory and 8/12 Kbyte RAM

STMicroelectronics 

Electrical characteristics

Figure 61. SSC master timing

SCLK

MTSR

MRST

1)

t300

t301 t302

2)

t304

t303

t305

t305

t306

1st out bit 2nd out bit

t307 t308

1st in bit

2nd In bit

ST10F271B/ST10F271E

t305

Last out bit

t307 t308

Last in bit

1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock

edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading

clock edge is low-to-high transition (SSCPO = 0b).

2. The bit timing is repeated for all bits to be transmitted or received.

Slave mode

VDD = 5V ±10%, VSS = 0V, TA = -40 to +125°C, CL = 50pF

Table 82. SSC slave mode timings

Symbol

Parameter

Max. Baudrate

6.6 MBd (1))

@FCPU = 40MHz

(<SSCBR> = 0002h)

Variable Baudrate

(<SSCBR> = 0001h -

FFFFh)

Unit

t310

SR SSC clock cycle time(2)

t311

SR SSC clock high time

t312

SR SSC clock low time

t313

SR SSC clock rise time

t314

SR SSC clock fall time

t315

CC Write data valid after shift edge

t316

CC Write data hold after shift edge

Read data setup time before latch

t317p

SR edge, phase error detection on

(SSCPEN = 1)

Read data hold time after latch

t318p

SR edge, phase error detection on

(SSCPEN = 1)

min.

150

63

63

–

–

–

0

62

87

max.

150

–

–

10

10

55

–

–

min.

max.

8TCL

262144 TCL ns

t310 / 2 – 12

–

ns

t310 / 2 – 12

–

ns

–

10

ns

–

10

ns

–

2TCL + 30 ns

0

–

ns

4TCL + 12

–

ns

–

6TCL + 12

–

ns

174/180

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