F272-BAR-P View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

F272-BAR-P

16-bit MCU with 256 Kbyte Flash memory and 12/20 Kbyte RAM

STMicroelectronics 

Electrical characteristics

ST10F272B/ST10F272E

Table 83. SSC slave mode timings (continued)

Symbol

Parameter

Max. Baudrate

6.6 MBd (1))

@FCPU = 40MHz

(<SSCBR> = 0002h)

Variable Baudrate

(<SSCBR> = 0001h -

FFFFh)

Unit

min.

max.

min.

max.

Read data setup time before latch

t317

SR edge, phase error detection off

6

(SSCPEN = 0)

Read data hold time after latch

t318

SR edge, phase error detection off

31

(SSCPEN = 0)

–

6

–

ns

–

2TCL + 6

–

ns

1. Maximum Baudrate is in reality 8Mbaud, that can be reached with 64MHz CPU clock and <SSCBR> set to ‘3h’, or with

48MHz CPU clock and <SSCBR> set to ‘2h’. When 40MHz CPU clock is used the maximum baudrate cannot be higher

than 6.6Mbaud (<SSCBR> = ‘2h’) due to the limited granularity of <SSCBR>. Value ‘1h’ for <SSCBR> may be used only

with CPU clock lower than 32MHz (after checking that resulting timings are suitable for the master).

2. Formula for SSC Clock Cycle time: t310 = 4 TCL * (<SSCBR> + 1)

Where <SSCBR> represents the content of the SSC Baudrate register, taken as unsigned 16-bit integer.

Minimum limit allowed for t310 is 125ns (corresponding to 8Mbaud).

Figure 61. SSC slave timing



3#,+

T

T T

T

T

T



T

T

-234

STOUTBIT NDOUTBIT

T T

T

,ASTOUTBIT

T T

-432

STINBIT

NDINBIT

,ASTINBIT

'!0'2)

1. The phase and polarity of shift and latch edge of SCLK is programmable. Figure 61 uses the leading clock

edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading

clock edge is low-to-high transition (SSCPO = 0b).

2. The bit timing is repeated for all bits to be transmitted or received.

182/188

Doc ID 11917 Rev 3

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