Electrical characteristics
ST10F273
24.8.20 High-speed synchronous serial interface (SSC) timing
Master mode
VDD = 5V ±10%, VSS = 0V, TA = -40°C to +125°C, CL = 50pF
Table 81. SSC master mode timings
Symbol
Parameter
Max.Baud rate 6.6MBd(1)
Variable Baud rate
@FCPU = 40 MHz
(<SSCBR> = 0002h)
(<SSCBR> = 0001h - FFFFh)
Min.
Max.
Min.
Max.
t300
CC SSC clock cycle time(2)
150
t301
CC SSC clock high time
63
t302
CC SSC clock low time
63
t303
CC SSC clock rise time
–
t304
CC SSC clock fall time
–
t305
CC Write data valid after shift edge
–
t306
CC Write data hold after shift edge(3)
–2
Read data setup time before latch
t307p SR edge, phase error detection on
(SSCPEN = 1)
37.5
150
8TCL
262144 TCL
–
t300 / 2 – 12
–
–
t300 / 2 – 12
–
10
–
10
10
–
10
15
–
15
–
–2
–
–
2TCL + 12.5
–
ns
Read data hold time after latch
t308p SR edge, phase error detection on
50
–
4TCL
–
(SSCPEN = 1)
Read data setup time before latch
t307
SR edge, phase error detection off
25
–
2TCL
–
(SSCPEN = 0)
Read data hold time after latch
t308
SR edge, phase error detection off
0
–
0
–
(SSCPEN = 0)
1. Maximum Baud rate is in reality 8Mbaud, that can be reached with 64 MHz CPU clock and <SSCBR> set to ‘3h’, or with 48
MHz CPU clock and <SSCBR> set to ‘2h’. When 40 MHz CPU clock is used the maximum baudrate cannot be higher than
6.6Mbaud (<SSCBR> = ‘2h’) due to the limited granularity of <SSCBR>. Value ‘1h’ for <SSCBR> can be used only with
CPU clock equal to (or lower than) 32 MHz.
2. Formula for SSC Clock Cycle time: t300 = 4 TCL x (<SSCBR> + 1) Where <SSCBR> represents the content of the SSC
Baudrate register, taken as unsigned 16-bit integer. Minimum limit allowed for t300 is 125ns (corresponding to 8Mbaud)
3. Partially tested, guaranteed by design characterization
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