ST10F273 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST10F273

16-bit MCU with 512 Kbyte Flash memory and 36 Kbyte RAM

STMicroelectronics 

ST10F273

Figure 59. SSC master timing

SCLK

MTSR

MRST

1)

t300

t301 t302

2)

t304

t303

t305

t305

t306

1st out bit 2nd out bit

t307 t308

1st in bit

2nd In bit

Electrical characteristics

t305

Last out bit

t307 t308

Last in bit

1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock

edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading

clock edge is low-to-high transition (SSCPO = 0b).

2. The bit timing is repeated for all bits to be transmitted or received.

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