ST7265X View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST7265X

Low speed USB 8-bit MCU family with up to 32 KB Flash/ROM

STMicroelectronics 

ST7265x

6.2 RESET SEQUENCE MANAGER (RSM)

6.2.1 Introduction

The reset sequence manager includes three RE-

SET sources as shown in Figure 6.2.2:

s External RESET source pulse

s Internal LVD RESET (Low Voltage Detection)

s Internal WATCHDOG RESET

These sources act on the RESET pin and it is al-

ways kept low during the delay phase.

Figure 18. RESET Sequences

VDD

VIT+(LVD)

VIT-(LVD)

The RESET service routine vector is fixed at ad-

dresses FFFEh-FFFFh in the ST7 memory map.

The basic RESET sequence consists of 3 phases

as shown in Figure 18:

s Active Phase depending on the RESET source

s Min 512 CPU clock cycle delay (see Figure 20

and Figure 21

s RESET vector fetch

RUN

LVD

RESET

ACTIVE PHASE

RUN

SHORT EXT.

RESET

ACTIVE

PHASE

RUN

LONG EXT.

RESET

ACTIVE

PHASE

RUN

WATCHDOG

RESET

ACTIVE

PHASE

RUN

EXTERNAL

RESET

SOURCE

RESET PIN

WATCHDOG

RESET

tw(RSTL)out

th(RSTL)in

tw(RSTL)out

th(RSTL)in

DELAY

tw(RSTL)out

WATCHDOG UNDERFLOW

INTERNAL RESET (min 512 TCPU)

VECTOR FETCH

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