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STM32F050C4 View Datasheet(PDF) - STMicroelectronics

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Description
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STM32F050C4 Datasheet PDF : 97 Pages
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STM32F050xx
Functional overview
3.6
Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example on
failure of an indirectly used external crystal, resonator or oscillator).
Several prescalers allow the application to configure the frequency of the AHB and the APB
domains. The maximum frequency of the AHB and the APB domains is 48 MHz.
Figure 2. Clock tree
(3)
393#,+
&,)4&#,+
TO&LASHPROGRAMMINGINTERFACE
TO)#
TO)3
-(Z (3)
(3)2#

0,,32#
0,,-5,
37
(3)
0,,
X X 
0,,#,+
!(!"("
PRESCALER
X
(3%
  
   

#33
393#,+
(#,+

!0"
PRESCALER
    
TO!("BUS CORE
MEMORYAND$-!
TOCORTEX3YSTEMTIMER
&(#,+#ORTEXFREERUNNINGCLOCK
0#,+
TO!0"PERIPHERALS
)F!0"PRESCALER
 XELSEX
TO4)-  
  
/3#?/54
/3#?).
-(Z
(3%/3#
-(Z (3)
(3)2#
!$#
0RESCALER
 
TO!$#
-(ZMAX
/3#?).
/3#?/54

,3%/3#
 K(Z ,3%
24##,+
24#3%,;=
TO24#
0#,+
393#,+
(3)
,3%
TO53!24
-#/
,3)2#
K(Z
-AINCLOCK
OUTPUT
,3)
 0,,#,+
(3)
(3)
(3%
393#,+
,3)
,3%
-#/
TO)7$'
)7$'#,+
-36
Doc ID 023683 Rev 1
15/97

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