SAA9750H View Datasheet(PDF) - Philips Electronics
Part Name
Description
Manufacturer
SAA9750H Datasheet PDF : 24 Pages
| |||
Philips Semiconductors
Camera Digital Signal Processor
(CAMDSP)
Preliminary specification
SAA9750H
R channel gain control = 1 + R-----G---1---2[---6-8--:--0----]- (1)
B channel gain control = 1 + -B----G---1---[2---6-8--:--0---]-- (1)
U gain control for positive side = U-----G-----P--1---6-[---5---:--0---]-
U gain control for negative side = U-----G-----N--1----6[---5---:--0----]-
V gain control for positive side = V-----G-----P--1---6-[--5----:-0----]-
V gain control for negative side = V-----G-----N--1---6-[---5---:--0---]--
U matrix 1 gain control = U-----M-----3--[-2-5----:-0----]- (1)
U matrix 2 gain control = U-----N-----3-[--2-5---:--0---]-- (1)
V matrix 1 gain control = -V----M-----3-[--2-5---:--0----]- (1)
V matrix 2 gain control = V-----N----3--[--25----:-0----]- (1)
Table 27 SP polarity control
SP POLARITY CONTROL
SPP
Normal
H: Ye + Mg or Ye + Gr
0
L: Cy + Gr or Cy + Mg
Invert
H: Cy + Gr or Cy + Mg
1
L: Ye + Mg or Ye + Gr
Table 28 FH2 polarity control
FH2 POLARITY CONTROL
Normal
Invert
FHP
H: 2B-G
0
L: 2R-G
H: 2R-G
1
L: 2B-G
Table 29 Colour filter control
COLOUR FILTER
CONTROL
LPF1
LPF2
LPF
0 [1,1,3,3,4,4,4,4,3,3,1,1]/32
1 [−1,0,4,8,10,8,4,0,−1]/32
Table 30 HD and VD polarity control
HD AND VD POLARITY CONTROL
Normal
Invert
SHV
0
1
Table 31 Sub LPF control for false colour
SUB LPF CONTROL FOR FALSE COLOUR
Normal
Sub LPF
JGM
0
1
Threshold control for false colour suppress = TH7 to TH0.
White clip level control = 2 × WC7 to WC0.
Table 32 Y delay control
Y DELAY CONTROL
0 clock period
+1 clock period
+2 clock periods
+3 clock periods
YDL1
0
0
1
1
YDL0
0
1
0
1
Table 33 C delay control
C DELAY CONTROL
0 clock period
+1 clock period
+2 clock periods
+3 clock periods
CDL1
0
0
1
1
CDL0
0
1
0
1
(1) RG, BG, UM, UN, VM and VN are twos complement.
1996 Feb 16
19
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