UPD75112GF-XXX-3BE View Datasheet(PDF) - NEC => Renesas Technology
Part Name
Description
Manufacturer
UPD75112GF-XXX-3BE Datasheet PDF : 56 Pages
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µPD75112(A), 75116(A)
4. Memory Configuration
• Program Memory (ROM)
12160 × 8 bits (0000H to 2F7FH): µPD75112(A)
16256 × 8 bits (0000H to 3F7FH): µPD75116(A)
• 0000H to 0001H: Vector table for writing the
program start address by reset
• 0002H to 000BH: Vector table for writing the
program start address by interrupt
Figure 4-1 Program Memory Map (µPD75112(A))
• 0020H to 007FH: Table area to be referred to
by the GETI instruction
• Data Memory
• Data area
512 × 4 bits (000H to 1FFH)
• Peripheral hardware area
128 × 4 bits (F80H to FFFH)
Address
76
0
0000H MBE RBE Internal Reset Start Address (High-Order 6 Bits)
Internal Reset Start Address (Low-Order 8 Bits)
0002H MBE RBE INTBT/INT4 Start Address (High-Order 6 Bits)
INTBT/INT4 Start Address (Low-Order 8 Bits)
0004H MBE RBE INT0/INT1 Start Address
(High-Order 6 Bits)
INT0/INT1 Start Address
(Low-Order 8 Bits)
0006H MBE RBE INTSIO Start Address
(High-Order 6 Bits)
INTSIO Start Address
0008H MBE RBE INTT0 Start Address
INTT0 Start Address
000AH MBE RBE INTT1 Start Address
(Low-Order 8 Bits)
(High-Order 6 Bits)
(Low-Order 8 Bits)
(High-Order 6 Bits)
CALLF
! faddr
Instruction
Entry
Address
INTT1 Start Address
(Low-Order 8 Bits)
≈
0020H
007FH
≈ 0080H
07FFH
≈ 0800H
0FFFH
1000H
≈
1FFFH
2000H
≈
2F7FH
GETI Instruction Reference Table
≈
BRCB
! caddr
Instruction
Branch
Address
≈
≈
≈
BRCB !caddr Instruction
Branch Address
≈
BRCB !caddr Instruction
Branch Address
CALL !addr
Instruction
Subroutin
Entry
Address
BR !addr
Instruction
Branch
Address
BR $addr
Instruction
Relative
Branch Address
(-15 to +16)
Branch Address
Subroutine Entry
Address by GETI
Instruction
Remarks: In all other cases, the program can be
branched by the BR PCDE and BR PCXA
instructions to an address with only the
lower 8 bits of PC changed.
11
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