UPD75238GJ View Datasheet(PDF) - NEC => Renesas Technology
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Description
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UPD75238GJ Datasheet PDF : 190 Pages
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µPD75238
2. ARCHITECTURE AND MEMORY MAP OF THE µPD75238
The µPD75238 has three architectural features:
(a) Data memory bank configuration
(b) General register bank configuration
(c) Memory-mapped I/O
Each of these features is explained below.
2.1 DATA MEMORY BANK CONFIGURATION AND ADDRESSING MODES
As shown in Fig. 2-1, the data memory space of the µPD75238 contains a static RAM (928 words × 4 bits)
at addresses 000H to 19FH and 200H to 3FFH, a display data memory (96 words × 4 bits) at addresses 1A0H
to 1FFH, and peripheral hardware (such as I/O ports and timers) at addresses F80H to FFFH. To address a 12-
bit address in this data memory space, the µPD75238 uses such a memory bank configuration that the low-
order eight bits are specified with an instruction directly or indirectly, and the high-order four bits are used
to specify a memory bank (MB).
To specify a memory bank (MB), a memory bank enable flag (MBE) and memory bank select register (MBS)
are contained, allowing the addressing indicated in Fig. 2-1 and Table 2-1. (The MBS is a register used to select
a memory bank, and can be set to 0, 1, 2, 3, or 15. The MBE is a flag used to determine whether a memory
bank selected using the MBS register is to be enabled. The MBE is automatically saved or restored at the time
of interrupt processing or subroutine processing, so that it can be freely set in interrupt processing and
subroutine processing.)
In addressing data memory space, the MBE is usually set to 1 (MBE = 1), and the static RAM in the memory
bank specified by the MBS is operated. However, the MBE = 0 mode or the MBE = 1 mode can be selected
for each step of program processing for more efficient programming.
MBE = 0 mode
MBE = 1 mode
Applicable program processing
• Interrupt processing
• Processing that repeats internal hardware and static RAM operations
• Subroutine processing
• Usual program processing
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