STA304 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STA304 Datasheet PDF : 30 Pages
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STA304
This interface support 4 sampling frequencies, according to the Variable and Double Rate Audio Codec `97
specification. The following table summarize the slot usage for each one the these frequencies:
Freq. Slot 3 Slot 4 Slot 6 Slot 7 Slot 8 Slot 9 Slot 10
Slot 11
Slot 12
48
Left Right Center Surr.L Surr.R LFE
44.1
Left Right
Surr.L Surr.R
88.2 * Left Right Center
Left (n+1) Right (n+1) Center (n+1)
96
Left Right Center
Left (n+1) Right (n+1) Center (n+1)
* Slots 3, 4 and 6 are always requested. Slots 10, 11 and 12 are requested only when needed.
The following table summarize the different input possibilities:
Input from
Channels
Available Freq. (KHz)
Bypass
Notes
I2S (Master)
4
48
Yes Bypass is user selectable
I2S (Slave)
4
32..96
No
S/PDIF
2
32..96
No
AC`97
6
48
Yes * Left, Right, SL, SR, Center, LFE
AC`97
3
96
No
Left, Right, Center
AC`97
4
44.1 (VRA)
No
Left, Right, SL, SR
AC`97
3
88.2 (VRA)
No
Left, Right, Center
* In this configuration the BYPASS is always active, regardless SRC_Bypass bit in reg. 5Ah
8.0 PLL
In order to generate the internal 49.152 MHz clock a low-jitter PLL has been included in the device. It can be config-
ured to work either with a multiplication factor of x8 or x2, in order to fit an external frequency reference of 6.144 MHz
or, respectively, 24.576 MHz. This could be useful when the device is configured to work in AC`97 slave mode where
the master clock is 24.576 MHz. To select the multiplication factor the PLL_Factor bit can be used.
Using the PLL_Bypass bit the PLL section can be bypassed, allowing direct connection of the internal clock to
the XTI pin. When this option is selected an external frequency of 49.152 MHz should be provided to the device.
In this condition the PLL is automatically powered-down.
9.0 POWERDOWN MANAGEMENT
The powerdown capability and its logic behaviour is shown in Figure 7 - Powerdown management . Basically
there are three powerdown requests which comes from the extern of the device and will cause a different pow-
erdown condition:
- External PWDN pin – this signal will turn-off the device which, as a consequence, will enter the power-
down mode (all the device clocks are stopped). The device will exit this state as soon as the PWDN pin
is deasserted.
- PR5 bit (reg. 26h, bit 13) – Setting this bit will cause a partial powerdown of the device: infact all the clocks
will be suspended, except that used to keep the AC97 and I2C cells alive. In this way, using either of these
input interfaces, it’ll be possible to resume from this state simply resetting the PR5 bit.
- EAPD bit (reg.26h, bit 15) – The External Amplifier PowerDown bit controls the state of the related pin
(EAPD) which, in turn, is used to switch off the external power chip.
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