DSP16410C View Datasheet(PDF) - Agere -> LSI Corporation

Part Name

Description

Manufacturer

DSP16410C

Digital Signal Processor

Agere -> LSI Corporation 

DSP16410C Digital Signal Processor

Data Addendum

May 2001

Contents

Table of Contents

Page

1 Introduction ................................................................................................................................................ 1

2 Features ..................................................................................................................................................... 1

3 Device Identification ................................................................................................................................... 1

4 Notation Conventions................................................................................................................................. 6

5 Ball Grid Array Information......................................................................................................................... 7

5.1 208-Ball PBGA Package .................................................................................................................. 7

5.2 256-Ball EBGA Package ................................................................................................................ 10

6 Device Characteristics ............................................................................................................................. 13

6.1 Absolute Maximum Ratings............................................................................................................ 13

6.2 Handling Precautions ..................................................................................................................... 13

6.3 Recommended Operating Conditions ............................................................................................ 14

6.3.1 Package Thermal Considerations .......................................................................................... 14

7 Electrical Characteristics and Requirements ........................................................................................... 15

7.1 Maintenance of Valid Logic Levels for Bidirectional Signals and Unused Inputs ........................... 17

7.2 Analog Power Supply Decoupling .................................................................................................. 18

7.3 Power Dissipation........................................................................................................................... 19

7.3.1 Internal Power Dissipation...................................................................................................... 19

7.3.2 I/O Power Dissipation............................................................................................................. 20

7.4 Power Supply Sequencing Issues .................................................................................................. 21

7.4.1 Supply Sequencing Recommendations ................................................................................. 21

7.4.2 External Power Sequence Protection Circuits........................................................................ 23

8 Timing Characteristics and Requirements ............................................................................................... 24

8.1 Phase-Lock Loop ........................................................................................................................... 25

8.2 Wake-Up Latency ........................................................................................................................... 25

8.3 DSP Clock Generation ................................................................................................................... 26

8.4 Reset Circuit ................................................................................................................................... 27

8.5 Reset Synchronization.................................................................................................................... 28

8.6 JTAG .............................................................................................................................................. 29

8.7 Interrupt and Trap........................................................................................................................... 30

8.8 Bit I/O ............................................................................................................................................. 31

8.9 System and External Memory Interface ......................................................................................... 32

8.9.1 Asynchronous Interface.......................................................................................................... 33

8.9.2 Synchronous Interface ........................................................................................................... 36

8.9.3 ERDY Interface ...................................................................................................................... 38

8.10 PIU ................................................................................................................................................. 39

8.11 SIU ................................................................................................................................................. 43

9 Package Diagrams................................................................................................................................... 53

9.1 208-Pin PBGA ................................................................................................................................ 53

9.2 256-Pin EBGA ................................................................................................................................ 54

2

Agere Systems Inc.

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