DSP16410C View Datasheet(PDF) - Agere -> LSI Corporation

Part Name

Description

Manufacturer

DSP16410C

Digital Signal Processor

Agere -> LSI Corporation 

Data Addendum

May 2001

DSP16410C Digital Signal Processor

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208-Ball PBGA Package Ball Grid Array Assignments (See-Through Top View)................................ 7

256-Ball EBGA Package Ball Grid Array Assignments (See-Through Top View).............................. 10

Plot of VOH vs. IOH Under Typical Operating Conditions .................................................................... 16

Plot of VOL vs. IOL Under Typical Operating Conditions ..................................................................... 16

Analog Supply Bypass and Decoupling Capacitors ........................................................................... 18

Power Supply Sequencing Recommendations .................................................................................. 22

Power Supply Example ...................................................................................................................... 23

Reference Voltage Level for Timing Characteristics and Requirements for Inputs and Outputs ....... 24

I/O Clock Timing Diagram ................................................................................................................. 26

Powerup and Device Reset Timing Diagram .................................................................................... 27

Reset Synchronization Timing............................................................................................................ 28

JTAG I/O Timing Diagram ................................................................................................................. 29

Interrupt and Trap Timing Diagram .................................................................................................... 30

Write Outputs Followed by Read Inputs (cbit = IMMEDIATE; a1 = sbit) Timing Characteristics ...... 31

Enable and Write Strobe Transition Timing........................................................................................ 32

Timing Diagram for EREQN and EACKN........................................................................................... 33

Asynchronous Read Timing Diagram (RHOLD = 0 and RSETUP = 0).............................................. 34

Asynchronous Write Timing Diagram (WHOLD = 0, WSETUP = 0) .................................................. 35

Synchronous Read Timing Diagram (Read-Read-Write Sequence).................................................. 36

Synchronous Write Timing Diagram................................................................................................... 37

ERDY Pin Timing Diagram................................................................................................................. 38

Host Data Write to PDI Timing Diagram............................................................................................. 39

Host Data Read from PDO Timing Diagram ...................................................................................... 40

Host Register Write (PAH, PAL, PCON, or HSCRATCH) Timing Diagram ........................................ 41

Host Register Read (PAH, PAL, PCON, or DSCRATCH) Timing Diagram........................................ 42

SIU Passive Frame and Channel Mode Input Timing Diagram.......................................................... 43

SIU Passive Frame Mode Output Timing Diagram ............................................................................ 44

SIU Passive Channel Mode Output Timing Diagram ......................................................................... 45

SCK External Clock Source Input Timing Diagram ............................................................................ 46

SIU Active Frame and Channel Mode Input Timing Diagram ............................................................ 47

SIU Active Frame Mode Output Timing Diagram ............................................................................... 49

SIU Active Channel Mode Output Timing Diagram ............................................................................ 50

ST-Bus 2x Input Timing Diagram ....................................................................................................... 51

ST-Bus 2x Output Timing Diagram .................................................................................................... 52

Agere Systems Inc.

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