DSP16410C View Datasheet(PDF) - Agere -> LSI Corporation

Part Name

Description

Manufacturer

DSP16410C

Digital Signal Processor

Agere -> LSI Corporation 

DSP16410C Digital Signal Processor

Data Addendum

May 2001

Table

List of Tables

Page

Table 1. Device Identifiers.......................................................................................................................................1

Table 2. 208-Ball PBGA Ball Assignments Sorted Alphabetically by Symbol.........................................................8

Table 3. 256-Ball EBGA Ball Assignments Sorted Alphabetically by Symbol.......................................................11

Table 4. Absolute Maximum Ratings for Supply Pins ...........................................................................................13

Table 5. Recommended Operating Conditions.....................................................................................................14

Table 6. Package Thermal Considerations ...........................................................................................................14

Table 7. Electrical Characteristics and Requirements ..........................................................................................15

Table 8. Internal Power Dissipation at 1.575 V .....................................................................................................19

Table 9. I/O Power Dissipation at 3.3 V ................................................................................................................20

Table 10. Power Sequencing Recommendations ...................................................................................................22

Table 11. Reference Voltage Level for Timing Characteristics and Requirements for Inputs and Outputs.............24

Table 12. PLL Requirements ..................................................................................................................................25

Table 13. Wake-Up Latency....................................................................................................................................25

Table 14. Timing Requirements for Input Clock......................................................................................................26

Table 15. Timing Characteristics for Input Clock and Output Clock........................................................................26

Table 16. Timing Requirements for Powerup and Device Reset.............................................................................27

Table 17. Timing Characteristics for Device Reset .................................................................................................27

Table 18. Timing Requirements for Reset Synchronization Timing ........................................................................28

Table 19. Timing Requirements for JTAG I/O .........................................................................................................29

Table 20. Timing Characteristics for JTAG I/O ........................................................................................................29

Table 21. Timing Requirements for Interrupt and Trap ...........................................................................................30

Table 22. Timing Requirements for BIO Input Read ...............................................................................................31

Table 23. Timing Characteristics for BIO Output ....................................................................................................31

Table 24. Timing Characteristics for Memory Enables and ERWN ........................................................................32

Table 25. Timing Requirements for EREQN ...........................................................................................................33

Table 26. Timing Characteristics for EACKN and SEMI Bus Disable .....................................................................33

Table 27. Timing Requirements for Asynchronous Memory Read Operations.......................................................34

Table 28. Timing Characteristics for Asynchronous Memory Read Operations .....................................................34

Table 29. Timing Characteristics for Asynchronous Memory Write Operations .....................................................35

Table 30. Timing Requirements for Synchronous Read Operations.......................................................................36

Table 31. Timing Characteristics for Synchronous Read Operations .....................................................................36

Table 32. Timing Characteristics for Synchronous Write Operations .....................................................................37

Table 33. Timing Requirements for ERDY Pin ........................................................................................................38

Table 34. Timing Requirements for PIU Data Write Operations .............................................................................39

Table 35. Timing Characteristics for PIU Data Write Operations............................................................................39

Table 36. Timing Requirements for PIU Data Read Operations .............................................................................40

Table 37. Timing Characteristics for PIU Data Read Operations............................................................................40

Table 38. Timing Requirements for PIU Register Write Operations .......................................................................41

Table 39. Timing Characteristics for PIU Register Write Operations ......................................................................41

Table 40. Timing Requirements for PIU Register Read Operations .......................................................................42

Table 41. Timing Characteristics for PIU Register Read Operations......................................................................42

Table 42. Timing Requirements for SIU Passive Frame Mode Input ......................................................................43

Table 43. Timing Requirements for SIU Passive Channel Mode Input ...................................................................43

Table 44. Timing Requirements for SIU Passive Frame Mode Output ...................................................................44

Table 45. Timing Characteristics for SIU Passive Frame Mode Output ..................................................................44

Table 46. Timing Requirements for SIU Passive Channel Mode Output ................................................................45

Table 47. Timing Characteristics for SIU Passive Channel Mode Output...............................................................45

Table 48. Timing Requirements for SCK External Clock Source............................................................................46

Table 49. Timing Requirements for SIU Active Frame Mode Input.........................................................................47

Table 50. Timing Characteristics for SIU Active Frame Mode Input .......................................................................47

Table 51. Timing Requirements for SIU Active Channel Mode Input......................................................................48

4

Agere Systems Inc.

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