ADV7175 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADV7175 Datasheet PDF : 36 Pages
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ADV7175/ADV7176
MPU PORT DESCRIPTION
The ADV7175 and ADV7176 support a two wire serial (I2C
compatible) microprocessor bus driving multiple peripherals.
Two inputs serial data (SDATA) and serial clock (SCLOCK)
carry information between any device connected to the bus.
Each slave device is recognized by a unique address. The
ADV7175 and ADV7176 each have four possible slave ad-
dresses for both read and write operations. These are unique
addresses for each device and are illustrated in Figure 26 and
Figure 27. The LSB sets either a read or write operation.
Logic Level “1” corresponds to a read operation while Logic
Level “0” corresponds to a write operation. A1 is set by setting
the ALSB pin of the ADV7175/ADV7176 to Logic Level “0” or
Logic Level “1.”
1
1
0
1
0
1
A1
X
ADDRESS
CONTROL
SET UP BY
ALSB
READ / W RITE
CONTROL
0
WRITE
1
READ
Fig 26. ADV7175 Slave Address
0
1
0
1
0
1
A1
X
ADDRESS
CONTROL
SET UP BY
ALSB
READ / W RITE
CONTROL
0
WRITE
1
READ
Fig 27. ADV7176 Slave Address
To control the various devices on the bus the following protocol
must be followed. First the master initiates a data transfer by es-
tablishing a start condition, defined by a high to low transition
on SDATA while SCLOCK remains high. This indicates that
an address/data stream will follow. All peripherals respond to
the start condition and shift the next eight bits (7-bit address +
R/W bit). The bits transferred from MSB down to LSB. The
peripheral that recognizes the transmitted address responds by
pulling the data line low during the ninth clock pulse. This is
known as an acknowledge bit. All other devices withdraw from
the bus at this point and maintain an idle condition. The idle
condition is where the device monitors the SDATA and SCLOCK
lines waiting for the Start condition and the correct transmitted
address. The R/W bit determines the direction of the data. A
Logic “0” on the LSB of the first byte means that the master
will write information to the peripheral. A Logic “1” on the
LSB of the first byte means that the master will read informa-
tion from the peripheral.
The ADV7175/ADV7176 acts as a standard slave device on the
bus. The data on the SDATA pin is 8 bits long supporting the
7-bit addresses plus the R/W bit. The ADV7175 has 33 sub-
addresses and the ADV7176 has 19 subaddresses to enable ac-
cess to the internal registers. It, therefore, interprets the first
byte as the device address and the second byte as the starting
subaddress. The subaddresses auto increment allowing data to
be written to or from the starting subaddress. A data transfer is
always terminated by a stop condition. The user can also access
any unique subaddress register on a one by one basis without
having to update all the registers. There is one exception. The
Subcarrier Frequency Registers should be updated in sequence,
starting with Subcarrier Frequency Register 0. The auto incre-
ment function should be then used to increment and access
subcarrier frequency registers 1, 2 and 3. The subcarrier fre-
quency registers should not be accessed independently.
Stop and start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of se-
quence with normal read and write operations, then these cause
an immediate jump to the idle condition. During a given
SCLOCK high period the user should only issue one start con-
dition, one stop condition or a single stop condition followed by
a single start condition. If an invalid subaddress is issued by the
user, the ADV7175/ADV7176 will not issue an acknowledge
and will return to the idle condition. If in auto-increment
mode, the user exceeds the highest subaddress then the follow-
ing action will be taken:
1. In Read Mode the highest subaddress register contents will
continue to be output until the master device issues a no-ac-
knowledge. This indicates the end of a read. A no-acknowledge
condition is where the SDATA line is not pulled low on the
ninth pulse.
2. In Write Mode, the data for the invalid byte will be not be
loaded into any subaddress register, a no-acknowledge will
be issued by the ADV7175/ADV7176 and the part will re-
turn to the idle condition.
Figure 28 illustrates an example of data transfer for a read se-
quence and the start and stop conditions.
SDATA
SCLOCK S
1-7 8 9
1-7 8 9
START ADDR R/W ACK SUBADDRESS ACK
1-7 8
DATA
9
ACK
P
STOP
Figure 28. Bus Data Transfer
Figure 29 shows bus write and read sequences.
WRITE
SEQUENCE
S SLAVE ADDR A(S)
SUB ADDR
A(S)
LSB = 0
DATA
A(S)
LSB = 1
DATA
A(S) P
READ
SEQUENCE
S SLAVE ADDR A(S) SUB ADDR A(S) S SLAVE ADDR A(S)
DATA
A(M)
S = START BIT
P = STOP BIT
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
A(S) = NO-ACKNOWLEDGE BY SLAVE
A(M) = NO-ACKNOWLEDGE BY MASTER
DATA
A(M) P
Figure 29. Write and Read Sequences
–16–
REV. A
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