SST25PF080B
4.8.5 WRITE-STATUS-REGISTER (WRSR)
The Write-Status-Register instruction writes new val-
ues to the BP2, BP1, BP0, and BPL bits of the status
register. CE# must be driven low before the command
sequence of the WRSR instruction is entered and
driven high before the WRSR instruction is executed.
See Figure 4-17 for EWSR or WREN and WRSR
instruction sequences.
Executing the Write-Status-Register instruction will be
ignored when WP# is low and BPL bit is set to “1”.
When the WP# is low, the BPL bit can only be set from
“0” to “1” to lock-down the status register, but cannot be
reset from “1” to “0”. When WP# is high, the lock-down
function of the BPL bit is disabled and the BPL, BP0,
BP1, and BP2 bits in the status register can all be
changed. As long as BPL bit is set to 0 or WP# pin is
driven high (VIH) prior to the low-to-high transition of the
CE# pin at the end of the WRSR instruction, the bits in
the status register can all be altered by the WRSR
instruction. In this case, a single WRSR instruction can
set the BPL bit to “1” to lock down the status register as
well as altering the BP0, BP1, and BP2 bits at the same
time. See Table 4-1 for a summary description of WP#
and BPL functions.
CE#
MODE 3
SCK MODE 0
0 123456 7
SI
50 or 06
MSB
SO
MODE 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MODE 0
01
MSB
HIGH IMPEDANCE
STATUS
REGISTER IN
76543210
MSB
25137 EWSR.0
FIGURE 4-17:
ENABLE-WRITE-STATUS-REGISTER (EWSR) OR WRITE-ENABLE (WREN) AND
WRITE-STATUS-REGISTER (WRSR) SEQUENCE
DS25134A-page 16
2012 Microchip Technology Inc.