CXD1961Q View Datasheet(PDF) - Sony Semiconductor

Part Name

Description

Manufacturer

CXD1961Q

DVB-S Front-end IC (QPSK demodulator + FEC)

Sony Semiconductor 

CXD1961Q

(4)Clock Recovery

Initial sampling clock frequency is set by a 24 bit word via the CPU I/F. This 24 bit word is written to the

NCO(Numerically Controlled Oscillator).

The sampling frequency is:

Fsample= 8*NCO [23:0]*Fxtal/224

where: NCO [23:0] is the parameter for sampling frequency, "8" is the divider gain of the PLL, Fxtal is the

reference crystal frequency, whose value should be more than 30MHz (32MHz is recommended).

The internal digital clock recovery loop feeds clock error data to the above NCO to provide sampling timing

correction .

AK [2:1] is the Loop Filter coefficient and CE_LEV [1:0] is the Loop Gain.

This value limits clock recovery range and resolution. (see the CPU Interface Register

Brief Explanation Fig.7)

Sampling clock is output from CKV (pin 69).

CPU I/F Register

AK [2:1] → ADD 7h

CE_LEV [1:0] → ADD 8h

NCO [23:0] → ADD D, E, Fh

(Example)

CE_LEV [1:0]=(0,1), NCO [23:0]=(001110000000000000000000), Fxtal=32 MHz

Sampling Frequency

= 8*(221+220+219)*32*106/224

= 23*7*106 = 56*106

→

56 MHz

Clock recovery range

= 29/(221+220+219)

= 1/210/7 = 139.5..*10–6

→

±140 ppm

Clock recovery

= 8*21*32*106/224 = 30.5. . . →

31 Hz

resolution

(5)Carrier Recovery

The Analog I/Q inputs have a carrier offset frequency, which is not corrected by the tuner's PLL

Synthesizer. The offset is compensated by a Costas Loop, using a frequency multiplier, loop filter and the

NCO. AC [2:1] is the coefficient of the loop filter and BC [2:1] is the loop gain parameter. QPSK

synchronization(QSYNC) is determined by monitoring the output of loop filter. The internal sync detector

monitors 256 cycles, and checks the value with the threshold set by QS_N [3:0]. In QPSK synchronization,

AFC [3:0] indicates the offset proportional value which remains at that point. This value is the average data

of the loop filter output. If AFC3(=MSB) is high, tuner PLL has a negative offset to the carrier frequency ,

and vice versa if AFC3 is low. By feeding the AFC [3:0] to the tuner's PLL Synthesizer, carrier offset can be

corrected with the PLL step size.

CPU I/F Register

QSYNC,AFC [3:0] → ADD 3h

QS_N [3:0], AC [2:1], BC [2:1] → ADD 6h

—12—

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