CXD1961Q View Datasheet(PDF) - Sony Semiconductor
Part Name
Description
Manufacturer
CXD1961Q Datasheet PDF : 15 Pages
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CXD1961Q
(10) Output Data Format
The following figure shows the output format of BYTCLK, PKTCLK, PKTERR. BYTCLK is generated by
dividing the internal viterbi clock by 8. Data output DATA[7:0] is output in sync with BYTCLK. DOUT_INV
determines whether DATA[7:0] is output on the rising edge or the falling edge of BYTCLK. PKTCLK High-
Time is equal to 188 data bytes period and PKTCLK Low-Time is equal to 16 parity bytes period. PKTERR
goes H if an uncorrectable error packet is encountered.
CPU I/F Register
DOUT_INV → ADD 9h
no error
data
parity
correctable error
data
parity
uncorrectable error
data
pa
BYTCLK
PKTCLK
PKTERR
BYTCLK and PKTCLK have varying forms, depending on the punctured rate. The following figure shows
Minimum and Maximum values for each rate.
One unit represents 1 sampling clock (=2∗Symbol rate) cycles.
Period
Min. Max.
R=1/2 16 16
R=2/3 12 12
R=3/4 10 11
R=4/5 10 10
R=5/6
9
10
R=6/7
9
10
R=7/8
9
10
(For example)
BYTCLK
High-Time
Min. Max.
8
8
6
6
5
6
5
5
4
5
4
5
4
5
Low-Time
Min. Max.
8
8
6
6
5
6
5
5
4
5
4
5
4
5
Period
Min. Max.
3264 3264
2448 2448
2176 1276
2040 2040
1948 1949
1904 1904
1865 1866
PKTCLK
High-Time
Min. Max.
3008 3008
2256 2256
2005 2006
1880 1880
1804 1805
1754 1755
1718 1719
Low-Time
Min. Max.
256 256
192 192
170 171
160 160
153 154
149 150
146 147
SACLK
R=1/2
Viterbi
clock
Byteclock
R=7/8
Viterbi
clock
Byte clock
—14—
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