LTC4263IDE View Datasheet(PDF) - Linear Technology

Part Name

Description

Manufacturer

LTC4263IDE

14-Bit, 65Msps ADC

Linear Technology 

LTC2205-14

APPLICATIONS INFORMATION

VTHRESHOLD = 1.6V

ENC+

1.6V ENC– LTC2205-14

0.1μF

220514 F09

Figure 9. Single-Ended ENC Drive,

Not Recommended for Low Jitter

3.3V

MC100LVELT22 3.3V 130Ω

Q0

D0

130Ω

ENC+

Q0

83Ω

ENC– LTC2205-14

83Ω

220514 F10

Figure 10. ENC Drive Using a CMOS to PECL Translator

Maximum and Minimum Encode Rates

The maximum encode rate for the LTC2205-14 is 65Msps.

For the ADC to operate properly the encode signal should

have a 50% (±2.5%) duty cycle. Achieving a precise 50%

duty cycle is easy with differential sinusoidal drive using

a transformer or using symmetric differential logic such

as PECL or LVDS. When using a single-ended ENCODE

signal asymmetric rise and fall times can result in duty

cycles that are far from 50%.

An optional clock duty cycle stabilizer can be used if the

input clock does not have a 50% duty cycle. This circuit

uses the rising edge of ENC pin to sample the analog input.

The falling edge of ENC is ignored and an internal falling

edge is generated by a phase-locked loop. The input clock

duty cycle can vary from 30% to 70% and the clock duty

cycle stabilizer will maintain a constant 50% internal duty

cycle. If the clock is turned off for a long period of time,

the duty cycle stabilizer circuit will require one hundred

clock cycles for the PLL to lock onto the input clock. To

use the clock duty cycle stabilizer, the MODE pin must be

connected to 1/3VDD or 2/3VDD using external resistors.

The lower limit of the LTC2205-14 sample rate is determined

by droop of the sample and hold circuits. The pipelined

architecture of this ADC relies on storing analog signals on

small valued capacitors. Junction leakage will discharge

the capacitors. The specified minimum operating frequency

for the LTC2205-14 is 1Msps.

DIGITAL OUTPUTS

Digital Output Buffers

Figure 11 shows an equivalent circuit for a single output

buffer. Each buffer is powered by OVDD and OGND, isolated

from the ADC power and ground. The additional N-channel

transistor in the output driver allows operation down to

low voltages. The internal resistor in series with the output

eliminates the need for external damping resistors.

As with all high speed/high resolution converters, the

digital output loading can affect the performance. The

digital outputs of the LTC2205-14 should drive a minimum

capacitive load to avoid possible interaction between the

digital outputs and sensitive input circuitry. The output

should be buffered with a device such as a ALVCH16373

CMOS latch. For full speed operation the capacitive load

should be kept under 10pF. A resistor in series with the

output may be used but is not required since the ADC has

a series resistor of 33Ω on chip.

Lower OVDD voltages will also help reduce interference

from the digital outputs.

LTC2205-14

VDD

DATA

FROM

LATCH

PREDRIVER

LOGIC

OVDD 0.5V

VDD

TO 3.6V

0.1μF

OVDD

33Ω

TYPICAL

DATA

OUTPUT

OGND

220514 F11

Figure 11. Equivalent Circuit for a Digital Output Buffer

20

220514fb

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