M2S56D20AKP View Datasheet(PDF) - Elpida Memory, Inc
Part Name
Description
Manufacturer
M2S56D20AKP Datasheet PDF : 41 Pages
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DDR SDRAM
E0338M10 (Ver.1.0)
(Previous Rev.1.54E)
Jan. '03 CP(K)
M2S56D20/ 30/ 40ATP
M2S56D20/ 30/ 40AKT
256M Double Data Rate Synchronous DRAM
POWER ON SEQUENCE
The following power on sequences are necessary to guarantee the proper operations of the DDR SDRAM.
1. Apply VDD before or at the same time as VDDQ
2. Apply VDDQ before or at the same time as VTT & VREF
3. Maintain stable conditions for 200us after stable power and CLK are applied, assert NOP or DSEL
4. Issue Precharge command for all banks of the device
5. Issue EMRS to program proper functions
6. Issue MRS to configure the Mode Register and to reset the DLL
7. Issue 2 or more Auto Refresh commands
8. Maintain stable conditions for 200 cycle
After these sequences, the DDR SDRAM is in the idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by
configuring the mode register (MRS). The mode register stores these data
until the next MRS command, which may be issued when both banks are in
idle state. After tMRD from an MRS command, the DDR SDRAM is ready to
accept the new command.
CLK
/CLK
/CS
/RAS
/CAS
/WE
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 BA0
BA1
0 0 0 0 0 0 DR 0 LTMODE BT
BL
A11-A0
V
Latency
Mode
CL
000
001
010
011
100
101
110
111
/CAS Latency
R
R
2
R
R
R
2.5
R
0
NO
DLL Reset
1
YES
Burst
Length
BL
0 00
0 01
0 10
0 11
1 00
1 01
1 10
1 11
BT=0
R
2
4
8
R
R
R
R
BT=1
R
2
4
8
R
R
R
R
0
Burst Type
1
Sequential
Interleaved
R: Reserved for Future Use
15
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