M34282M1 View Datasheet(PDF) - Renesas Electronics
Part Name
Description
Manufacturer
M34282M1 Datasheet PDF : 69 Pages
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4282 Group
LIST OF PRECAUTIONS
➀ Noise and latch-up prevention
Connect a capacitor on the following condition to prevent noise
and latch-up;
• connect a bypass capacitor (approx. 0.01 µF) between pins
VDD and VSS at the shortest distance,
• equalize its wiring in width and length, and
• use the thickest wire.
In the One Time PROM version, port E2 is also used as VPP
pin. Connect this pin to VSS through the resistor about 5 kΩ
which is assigned to E2/VPP pin as close as possible at the
shortest distance.
➁ Notes on unused pins
(Note in order to set the output latch to “0” to make pins open)
• After system is released from reset, a port is in a high-
impedance state until the output latch of the port is set to
“0” by software.
Accordingly, the voltage level of pins is undefined and the
excess of the supply current may occur.
• To set the output latch periodically is recommended
because the value of output latch may change by noise or
a program run away (caused by noise).
(Note when connecting to VSS and VDD)
• Connect the unused pins to VSS and VDD at the shortest
distance and use the thick wire against noise.
➂ Timer
• Count source
Stop timer 1 or timer 2 counting to change its count source.
• Watchdog timer
Be sure that the timing to execute the WRST instruction in
order to operate WDT efficiently.
• Writing to reload register R1
When writing data to reload register R1 while timer 1 is
operating, avoid a timing when timer 1 underflows.
• Timer 1 count operation
When the bit 5 of the watchdog timer (WDT) is selected as
the timer 1 count source, the error of maximum ± 256 µs
(at the minimum instruction execution time : 8 µs) is
generated from timer 1 start until timer 1 underflow. When
programming, be careful about this error.
• Stop of timer 2
Avoid a timing when timer 2 underflows to stop timer 2.
• Writing to reload register R2H
When writing data to reload register R2H while timer 2 is
operating, avoid a timing when timer underflows.
• Timer 2 carrier wave output function
When to expand “H” interval of carrier wave is valid, set “1”
or more to reload register R2H.
➃ Program counter
Make sure that the program counter does not specify after the
last page of the built-in ROM.
➄ Power-on reset
Under the following condition, the system reset occurs by the
built-in the power-on reset circuit of this product;
- when the supply voltage (VDD) rises from 0 V to 2.2 V, within 1 ms.
Also, note that system reset does not occur under the following
conditions;
- when the supply voltage (VDD) rises from the voltage higher
than 0V, or
- when it takes more than 1 ms for the supply voltage (VDD) to
rise from 0 V to 2.2 V.
➅ Voltage drop detection circuit
The voltage drop detection circuit detection voltage of this
product is set up lower than the minimum value of the supply
voltage of the recommended operating conditions.
A battery exchange of an application product is explained as
an example.
The supply voltage falls below to the recommended operating
voltage while CPU keeps active. Then, an unexpected
oscillation-stop, which does not happen by POF instruction
occurs before the supply voltage falls below to the detection
voltage. In this time, even if the supply voltage re-goes up to
the recommended operating voltage, since reset does not
occur, MCU may not operate correctly.
Please confirm the oscillator you use and the frequency of
system clock, and test the operation of your system sufficiently.
VDD
Recommended operatng
condition min.value
VDET
Oscillation is stopped
incorrectly.
Even if the voltage re-goes up to
the recommended operating voltage,
MCU may not operate correctly.
VDD
Recommended
operatng condition
min.value
VDET
Fig. 28 VDD and VDET
Reset
→ Normal operation
Rev.1.33 Mar 18, 2004 page 22 of 67
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