MSP3410D View Datasheet(PDF) - Micronas

Part Name

Description

Manufacturer

MSP3410D

Multistandard Sound Processors

Micronas 

PRELIMINARY DATA SHEET

MSP 34x0D

Table 4–1: Some examples for recommended channel assignments for demodulator and audio processing part

Mode

B/G-Stereo

B/G-Bilingual

MSP Sound IF-

Channel 1

FM2 (5.74 MHz): R

FM2 (5.74 MHz): Sound B

NICAM-I-ST/

FM-mono

Sat-Mono

Sat-Stereo

Sat-Bilingual

NICAM (6.552 MHz)

not used

7.2 MHz: R

7.38 MHz: Sound C

Sat-High Dev.

Mode

don’t care

MSP Sound IF-

Channel 2

FM1 (5.5 MHz): (L+R)/2

FM1 (5.5 MHz): Sound A

FM (6.0 MHz): mono

FM (6.5 MHz): mono

7.02 MHz: L

7.02 MHz: Sound A

6.552 MHz

FM-

Matrix

B/G Stereo

No Matrix

No Matrix

No Matrix

No Matrix

No Matrix

No Matrix

Channel-

Select

Speakers: FM

Speakers: FM

H. Phone: FM

Speakers: NICAM

H. Phone: FM

Speakers: FM

Speakers: FM

Speakers: FM

H. Phone: FM

Speakers: FM

H. Phone: FM

Channel

Matrix

Stereo

Speakers: Sound A

H. Phone: Sound B

Speakers: Stereo

H. Phone: Sound A

Sound A

Stereo

Speakers: Sound A

H. Phone: Sound B=C

Speakers: Sound A

H. Phone: Sound A

4.4. Audio PLL and Crystal Specifications

The MSP 34x0D requires a 18.432 MHz (12 pF, paral-

lel) crystal. The clock supply of the whole system

depends on the MSP 34x0D operation mode:

1. FM-Stereo, FM-Mono:

The system clock runs free on the crystal’s

18.432 MHz.

2. NICAM:

An integrated clock PLL uses the 364 kHz baud

rate, accomplished in the NICAM demodulator block

to lock the system clock to the bit rate, respectively,

32-kHz sampling rate of the NICAM transmitter. As

a result, the whole audio system is supplied with a

controlled 18.432 MHz clock.

3. I2S slave operation:

In this case, the system clock is locked to a synchro-

nizing signal (I2S_CL, I2S_WS) supplied by the

coprocessor chip.

Remark on using the crystal:

External capacitors at each crystal pin to ground are

required (see General Crystal Recommendations on

page 69).

4.5. ADR Bus Interface

For the ASTRA Digital Radio System (ADR), the

MSP 34x0D performs preprocessing, as there are car-

rier selection and filtering. Via the 3-line ADR bus, the

resulting signals are transferred to the DRP 3510A,

where the source decoding is performed. To be pre-

pared for an upgrade to ADR with an additional DRP

board, the following lines of MSP 34x0D should be

provided on a feature connector:

– AUD_CL_OUT

– I2S_DA_IN1 or I2S_DA_IN2

– I2S_DA_OUT

– I2S_WS

– I2S_CLK

– ADR_CL

– ADR_WS

– ADR_DA

4.6. Digital Control Output Pins

The static level of two output pins of the MSP 34x0D

(D_CTR_OUT0/1) is switchable between HIGH and

LOW by means of the I2C bus. This enables the con-

trolling of external hardware-controlled switches or

other devices via I2C bus (see section 7.3.18. on page

47).

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