MSP3410D View Datasheet(PDF) - Micronas

Part Name

Description

Manufacturer

MSP3410D

Multistandard Sound Processors

Micronas 

MSP 34x0D

Table 5–3: Control Register (Subaddress: 00 hex)

Name

Subaddress

MSB

14

CONTROL

00 hex

1 : RESET

0

0 : normal

PRELIMINARY DATA SHEET

13..1

0

LSB

0

5.1. Protocol Description

Write to DSP or Demodulator

S

write

Wait ACK

device

address

subaddr

ACK addr byte ACK addr byte ACK data byte ACK data byte ACK P

high

low

high

low

Read from DSP or Demodulator

S write Wait ACK

device

address

subaddr

ACK addr byte ACK addr byte ACK S

high

low

read

device

address

Wait ACK data byte ACK data byte NAK P

high

low

Write to Control or Test Registers

S

write

Wait ACK

device

address

subaddr

ACK

data byte high

ACK

data byte low

ACK P

Note: S =

P=

ACK =

NAK =

Wait =

I2C bus Start Condition from master

I2C bus Stop Condition from master

Acknowledge-Bit: LOW on I2C_DA from slave (=MSP, gray)

or master (=CCU, hatched)

Not-Acknowledge Bit: HIGH on I2C_DA from master (=CCU, hatched) to indicate ‘End of Read’

or from MSP indicating internal error state

I2C clock line held low by the slave (=MSP) while interrupt is serviced (<1.8 ms)

I2C_DA

S

I2C_CL

Fig. 5–1: I2C bus protocol

1

0

P

(MSB first; data must be stable while clock is high)

18

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