PEB20321 View Datasheet(PDF) - Siemens AG

Part Name

Description

Manufacturer

PEB20321

Multichannel Network Interface Controller for HDLC MUNICH32X

Siemens AG 

PEB 20321

Introduction

1.2 New or Changed from MUNICH32, PEB 20320

• Symmetrical Rx and Tx Buffer Descriptor formats for faster switching

• Improved Tx idle channel polling process, which significantly reduces bus occupancy

of idle Tx channels

• Additional PCM modes supported: 3.088 Mbit/s, 6.176 Mbit/s, 8.192 Mbit/s

• 32-bit PCI bus Master/Slave interface (33 MHz) with integrated DMA controllers for

higher performance, and lower development effort and risk

• Enhanced Interrupt Structure providing:

separate serial PCM Rx and Tx Interrupt Queues in host memory,

separate DMA related LBI Rx and Tx Interrupt Queues in host memory,

dedicated LBI pass-through, SSC, General Purpose bus and IOM®-2 Peripheral

Interrupt Queue in host memory

• Slave read capability of serial PCM core, LBI, SSC and IOM®-2 read/write registers

• Time Slot Shift capability

programmable from -4 clock edges to +3 clock edges relative to synchronization

pulse,

programmable to sample Tx data at either clock falling or rising edge,

programmable to sample Rx data at either clock falling or rising edge,

• Software initiated Action Request via a bit field in the Command register

• Tx End-of-Packet transmitted-on-wire interrupt capability per channel

• Tx packet size increased to 16 Kbytes

• Rx packet size 8 kbyte limit interrupt disable

• Rx Enable bit field of the MODE1 register

• Rx Interrupt Disable bit field of the MODE1 register

• Tx data tristate control line (TXDEN)

• Synchronized data transfer in TMA mode for complete transparency when using

fractional T1/PRI channels

• Integrated Local Bus Interface (LBI), which allows connection to peripherals that do

not provide a PCI bus interface

• IOM®-2 interface with single and double data rate clock

• Collision control on S/T interface by QUAT-S (PEB 2084) via data ready control line

(DRDY)

• Synchronous Serial Control (SSC) interface

• 16-bit General Purpose Bus (available, when LBI and SSC are not used)

• Internal Descriptor and Table Dump capability for software development purposes

• Little/Big Endian data formats selectable via a bit field in Configuration register

Semiconductor Group

11

1998-08-01

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