SSD1818 View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

SSD1818

LCD Segment / Common Driver with Controller

Unspecified 

Read cycle

E( RD ) input serves as data read latch signal (clock) when low, provided that CS1 is pulled low and the

CS2 is pulled high respectively. The D/ C signal determines whether the receiving signal is a display data

read or a status register read signal. Similar to 6800-series interface, a dummy read is also required

before the first actual display data read.

Write cycle

R/ W ( WR ) input serves as data write latch signal(clock) when high, provided that CS1 and CS2 are low

and high respectively. The D/ C signal determines whether the receiving signal is a display data write or a

command register write signal.

Please refer to Figure 10 on Page 35 for Parallel Interface Timing Diagram of 8080-series microprocessor.

MPU Serial interface

The serial interface consists of serial clock SCK (D6), serial data SDA (D7), D/ C , CS1 and CS2. Input to

SDA is shifted into a 8-bit shift register on every rising edge of SCK in the order of D7, D6,... D0. D/ C is

sampled on every eighth clock to determine whether the data byte in the shift register is written to the

Display Data RAM or command register at the same clock.

Oscillator Circuit

This module is an On-Chip low power RC oscillator circuitry (Figure 4). The oscillator generates the clock

for the DC-DC voltage converter. This clock is also used in the Display Timing Generator.

Oscillator

enable

enable

enable

Oscillation Circuit

Buffer

(CL)

Internal resistor

OSC1

OSC2

Figure 4 - Oscillator

LCD Driving Voltage Generator and Regulator

This module generates the LCD voltage required for display driving output. With reference to VDD, it takes

a single supply input, VSS, and generate necessary voltage levels. This block consists of:

1. 2X, 3X, 4X and 5X DC-DC voltage converter

The built-in DC-DC voltage converter is used to generate the negative voltage with reference to VDD from

the voltage input (VSS1). For SSD1818, it is possible to produce 2X, 3X, 4X or 5X boosting from the

potential different between VSS1 - VDD. Detailed configurations of the DC-DC converter for different

boosting multiples are given in Figure 5.

13

SSD1818 Series

Rev 1.2

08/2002

SOLOMON

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