GDC21D601 View Datasheet(PDF) - Hynix Semiconductor

Part Name

Description

Manufacturer

GDC21D601

32-Bit RISC MCU

Hynix Semiconductor 

GDC21D601

Table 2. Static Memory Controller External Signal Descriptions

NAME

EXPRDY

EXPCLK

nWEN[3:0]

nWEF[3:0]

NSRAMOE

nCS[5:0]

CS[7:6]

SRAMA [1:0]

nSRAMALatch

MemByteSeq[1:0]

nSRAMOutLEn

nSRAMOutEn[1:0]

nSRAMInLEn[1:0]

nSRAMInEn

Mode[1:0]

TYPE

I

O

O

I

O

O

O

O

O

O

O

O

O

O

I

DESCRIPTION

Expansion channel ready. This signal is active LOW by default, When this

signal is LOW, it will force the current memory transfer to be extended. When

the RDON bit field in Configuration Register is set, then the polarity of the

EXPRDY signal is reversed to active HIGH.

Expansion clock output. Clock output at the same phase and speed as the bus

clock. Active only during SRAM/ROM cycles.

These signals are active LOW write enables for each of the memory byte lanes

on the external bus. For example nWEN[0] controls the writes to D[7:0].

These optional connections use PADs feedback from the external side of the

nWEN[3:0] PADs. They are used to guarantee address and chip select hold

time when any write enable is LOW. If not used, they should be tied to HIGH.

This is the active LOW output enable for devices on the external bus. This is

LOW during reads from external memory and during the time that the selected

bank should drive the external data bus.

Active LOW Chip Select

Active HIGH Chip Select

These signals form the lower two bits of the external address bus. They are

used to control accesses to 16- or 8-bit memories when the AMBA bus

requests an access size larger than the memory (this is handled using multiple

external transfers).

This signal is an active LOW transparent address latch enable. It is normally

HIGH to prevent power wasting transitions on the external address bus.

These signals control the data path muxes which allow 16- or 8-bit memories to

read and write 32-bit values on the AMBA bus.

Active LOW transparent latch enable for the data out path (writes).

Active LOW byte lane data output driver enable.

Active LOW transparent latch enable for the data in path (reads).

Active LOW data input driver enable (to AMBA bus).

Booting mode configuration input. If these signals are “00” during BnRES

LOW then the SRAM Controller will select bank zero (nCS[0]) as 32-bit

memory. If these signals are “10” then select bank zero as 16-bit memory. If

these signals are “01” then bank zero as 8-bit memory.

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