GDC21D601 View Datasheet(PDF) - Hynix Semiconductor

Part Name

Description

Manufacturer

GDC21D601

32-Bit RISC MCU

Hynix Semiconductor 

GDC21D601

Accesses to the Static Memory Controller module can be two basic types; control register accesses and memory

area accesses. The following timing diagrams relate to the external pin timings for SRAM/ROM read and write

cycles in minimum wait states.

BCLK

BTRAN[1:0]

N_TRAN

S_TRAN

S_TRAN

S_TRAN

S_TRAN

BA[23:0]

address n

address n+4

address n+8

DSELSRAM

BWAIT

BD[31:0]

EXPCLK

nCS[5:0]

nSRAMOE

A[23:0]

D[31:0]

EXPRDY

address n

address n+4

address n+8

Deocde

Wait

read

read

read

Figure 2. ROM Read Timing

41

Share Link: