MPC2605ZP66R View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

Manufacturer

MPC2605ZP66R

Integrated Secondary Cache for PowerPC Microprocessors

Motorola => Freescale 

READ HIT/WRITE HIT (WITHOUT CPU DBG PARKED)

Most of the previous examples have assumed CPU DBG

is asserted in the same cycle that the processor asserts TS.

This implies CPU DBG is parked. In some systems it may not

be desirable or possible to park CPU DBG. Figure 9 shows

the response for a read hit from the MPC2605 is gated by the

assertion of CPU DBG. The fastest response possible in a

system that does not park CPU DBG is 3–1–1–1.

CLK

CPU BG

1

2

3

4

5

6

7

TS

A0 – A31

A

TBST

L2 CLAIM

AACK

CPU DBG

DBB

TA

DH0 – DH31,

DL0 – DL31

A1

A2

A3

A4

LEGEND

Signal driven to the MPC2605

Signal driven by the MPC2605

High–Z

Figure 9. Burst Read (or Write) Hit Without CPU DBG Parked

MOTOROLA

MPC2605

23

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