MPC5200BDS View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

MPC5200BDS

SDRAM/DDR Memory Controller

Freescale Semiconductor 

• Input conditions:

All Inputs: tr, tf <= 1 ns

• Output Loading:

All Outputs: 50 pF

1.3.2 AC Operating Frequency Data

Table 12 provides the operating frequency information for the MPC5200B.

Table 12. Clock Frequencies

Min

Max

1

e300 Processor Core

—

400

2

SDRAM Clock

—

133

3

XL Bus Clock

—

133

4

IP Bus Clock

—

133

5

PCI / Local Plus Bus Clock

—

66

6

PLL Input Range

15.6

35

Units

MHz

MHz

MHz

MHz

MHz

MHz

SpecID

A1.1

A1.2

A1.3

A1.4

A1.5

A1.6

1.3.3 Clock AC Specifications

SYSCLK

t CYCLE

t DUTY

t DUTY

t RISE

VM

VM

VM

CV IH

CV IL

Figure 2. Timing Diagram—SYS_XTAL_IN

t FALL

Table 13. SYS_XTAL_IN Timing

Sym

Description

Min Max Units SpecID

t CYCLE

SYS_XTAL_IN cycle time.(1)

28.6 64.1

ns

A2.1

t RISE

SYS_XTAL_IN rise time.

—

5.0

ns

A2.2

t FALL

t DUTY

SYS_XTAL_IN fall time.

SYS_XTAL_IN duty cycle (measured at VM).(2)

—

5.0

ns

A2.3

40.0 60.0 %

A2.4

CV IH

SYS_XTAL_IN input voltage high

2.0

—

V

A2.5

CV IL

SYS_XTAL_IN input voltage low

—

0.8

V

A2.6

1 CAUTION—The SYS_XTAL_IN frequency and system PLL_CFG[0–6] settings must be chosen such that the resulting

system frequencies do not exceed their respective maximum or minimum operating frequencies. See the MPC5200B

User’s Manual (MPC5200BUM).

2 SYS_XTAL_IN duty cycle is measured at VM.

MPC5200B Data Sheet, Rev. 4

Freescale Semiconductor

13

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