MPC5200BDS View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

MPC5200BDS

SDRAM/DDR Memory Controller

Freescale Semiconductor 

MEM_CLK

Control Signals

DQM (Data Mask)

MDQ (Data)

MA (Address)

MBA (Bank Selects)

tvalid

thold

Active

NOP

DMvalid

READ NOP

DMhold

NOP NOP NOP

datasetup

tvalid

tvalid

Row

thold

thold

Column

datahold

NOP

NOTE: Control Signals are composed of RAS, CAS, MEM_WE, MEM_CS, MEM_CS1 and CLK_EN

Figure 5. Timing Diagram—Standard SDRAM Memory Read Timing

1.3.6.2 Memory Interface Timing-Standard SDRAM Write Command

In Standard SDRAM, all signals are activated on the MEM_CLK from the Memory Controller and captured on the MEM_CLK

clock at the memory device.

Table 19. Standard SDRAM Write Timing

Sym

tmem_clk

tvalid

thold

DMvalid

DMhold

datavalid

datahold

Description

Min

Max

Units SpecID

MEM_CLK period

7.5

—

ns

Control Signals, Address and MBA Valid

after rising edge of MEM_CLK

—

tmem_clk × 0.5 + 0.4 ns

Control Signals, Address and MBA Hold after

rising edge of MEM_CLK

tmem_clk × 0.5

—

ns

DQM valid after rising edge of MEM_CLK

—

tmem_clk × 0.25 + 0.4 ns

DQM hold after rising edge of Mem_clk tmem_clk × 0.25 – 0.7

—

ns

MDQ valid after rising edge of MEM_CLK

—

tmem_clk × 0.75 + 0.4 ns

MDQ hold after rising edge of MEM_CLK tmem_clk × 0.75 – 0.7

—

ns

A5.8

A5.9

A5.10

A5.11

A5.12

A5.13

A5.14

MPC5200B Data Sheet, Rev. 4

18

Freescale Semiconductor

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