K4B4G1646B View Datasheet(PDF) - Samsung

Part Name

Description

Manufacturer

K4B4G1646B

4Gb B-die DDR3 SDRAM

Samsung 

K4B4G1646B

datasheet

Rev. 1.0

DDR3 SDRAM

NOTE :Clock and Strobe are drawn on a different time scale.

tIS

tIH

CK

CK

DQS

tIS tIH

DQS

VDDQ

tDS tDH

VIH(AC) min

VREF to ac

region

VIH(DC) min

VREF(DC)

VIL(DC) max

nominal slew

rate

VIL(AC) max

VSS

tVAC

tDS tDH

tVAC

nominal

slew rate

VREF to ac

region

Δ TF

Setup Slew Rate

Falling Signal

=

VREF(DC) - VIL(AC)max

Δ TF

Δ TR

Setup Slew Rate

Rising Signal

=

VIH(AC)min - VREF(DC)

Δ TR

Figure 25. Illustration of nominal slew rate and tVAC for setup time tDS (for DQ with respect to strobe) and tIS

(for ADD/CMD with respect to clock).

- 62 -

Share Link: