K4B4G1646B View Datasheet(PDF) - Samsung

Part Name

Description

Manufacturer

K4B4G1646B

4Gb B-die DDR3 SDRAM

Samsung 

K4B4G1646B

datasheet

Rev. 1.0

DDR3 SDRAM

NOTE :Clock and Strobe are drawn on a different time scale.

tIS

tIH

CK

CK

DQS

tIS tIH

DQS

VDDQ

tDS tDH

nominal

line

VIH(AC) min

VREF to ac

region

VIH(DC) min

VREF(DC)

tangent

line

tDS tDH

tVAC

tangent

line

VIL(DC) max

VIL(AC) max

nominal

line

VSS

Δ TF

VREF to ac

region

tVAC

Δ TR

Setup Slew Rate

Rising Signal

=

tangent line[VIH(AC)min - VREF(DC)]

Δ TR

Setup Slew Rate

Falling Signal =

tangent line[VREF(DC) - VIL(AC)max]

Δ TF

Figure 27. Illustration of tangent line for setup time tDS (for DQ with respect to strobe) and tIS

(for ADD/CMD with respect to clock)

- 64 -

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